ZHCSKU1A February   2020  – July 2020 2N7001T-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     6
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Operating Characteritics: TA = 25°C
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Load Circuit and Voltage Waveforms
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Up-Translation or Down-Translation from 1.65 V to 3.60 V
      2. 8.3.2 Balanced CMOS Push-Pull Outputs
      3. 8.3.3 Standard CMOS Inputs
      4. 8.3.4 Negative Clamping Diodes
      5. 8.3.5 Partial Power Down (Ioff)
      6. 8.3.6 Over-voltage Tolerant Inputs
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Processor Error Up Translation
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Discrete FET Translation Replacement
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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订购信息

7.1 Load Circuit and Voltage Waveforms

Unless otherwise noted, all input pulses are supplied by generators having the following characteristics:

  • f = 1 MHz
  • ZO = 50 Ω
  • dv/dt ≤ 1 ns/V

GUID-2763F09A-1797-452C-B2AA-E1A41C47E9D1-low.gif
CL includes probe and jig capacitance.
Figure 7-1 Load Circuit
Table 7-1 Load Circuit Conditions
ParameterVCCRLCL
tpdPropagation (delay) time1.65 V – 3.6 V2 kΩ15 pF
GUID-737A6CD9-5A5F-4CC6-A8E1-60291B38F3C5-low.gif
VCCI is the supply pin associated with the input port.
VOH and VOL are typical output voltage levels that occur with specified RL and CL.
Figure 7-2 Propagation Delay
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