6.8.1 MSGMGR
The SoC implements a single instance of the Message Manager to provide inter-processor communication between the various processing units:
- Arm (Cortex-A15)
- DSP (C66x)
- PMMC (CPU)
- PRU-ICSS (PRUs)
The Message Manager is a hardware engine used for queuing messages in a secure and self-contained manner. There is no limitation on the message format or content. It is software responsibility to define the message format.
The Message Manager provides a multi-core and multi-process safe message interface which allows multiple users (message senders and receivers) to access the queues without the need for any mutual exclusion. It also allows for secure and authorized access to the queues.
The general features of the Message Manager module include:
- Provides hardware acceleration for pushing/popping messages to/from logical queues
- Supports the following SoC configuration:
- 64 queues
- Up to 128 pending messages
- 64-byte messages
- 32 proxies (single proxy per page)
- Support for highly-pipelined push/pop operations
- Support for self-contained mode with zero SW initialization
- Provides a secure front-end for the queues
- Provides flexible message allocation with ability to store the same message multiple times in different queues or multiple times in the same queue
- Queue depth limited only by the maximum number of messages
- Support for little-endian (LE) operation only
Monitoring and trace functions include:
- Provides hardware signals to monitor the empty status for all transmit source queues
- Provides ability to read Linking RAM contents for debug purposes
- Provides ability to generate an interrupt when there are no free entries in the Linking RAM
- Provides ability to generate an interrupt due to a proxy fault
For more information, see section Message Manager in chapter Interprocessor Communication of the Device TRM.