5.9.3.1 Input Clocks / Oscillators

Various external clock sources are required as timing references for the device. Specific clock requirements are based on use cases supported by the application. Summary of these input clock signals are:

• SYSOSC_IN / SYSOSC_OUT - system oscillator (SYSOSC) pins. SYSOSC is used to source the system reference clock (SYS_OSCCLK) when the SYSCLKSEL pin is low. The SYSOSC pins can be connected to the appropriate external crystal circuit or the oscillator can be bypassed when using an LVCMOS clock source connected to the SYSOSC_IN pin.

NOTE

When connecting SYSOSC_IN to an LVCMOS clock source, the LVCMOS clock source output must be disabled anytime SYSOSC is disabled since SYSOSC_IN has a strong internal pull-down resistor which is turned on when SYSOSC is disabled.

• SYSCLK_P / SYSCLK_N - optional system clock LVDS differential input. This input is used to source the system reference clock (SYS_OSCCLK) when the SYSCLKSEL pin is high.
• DDR_CLK_P / DDR_CLK_N - optional DDR/EMIF clock LVDS differential input. This input is used to produce a DDR PLL reference clock (DDR_CLK) when the DDR_CLK_MUXSEL bit is high.
• AUDOSC_IN / AUDOSC_OUT - optional audio oscillator (AUDIOOSC) pins. AUDIOOSC can be used to produce an audio reference clock (AUDIO_OSCCLK) which is one of several clock options for the McASPs and McBSP. When used, AUDIOOSC can be connected to the appropriate external crystal circuit or the oscillator can be bypassed when using an LVCMOS clock source connected to the AUDOSC_IN pin.

NOTE

When connecting AUDOSC_IN to an LVCMOS clock source, the LVCMOS clock source output must be disabled anytime AUDOSC is disabled since AUDOSC_IN has a strong internal pull-down resistor which is turned on when AUDIOOSC is disabled. This requires the LVCMOS clock source to be disabled by default and output enable controlled by software via a general purpose output since AUDIOOSC is disabled by default.

• PCIE_CLK_P / PCIE_CLK_N - PCIe reference clock LVDS differential input.
• USB0_XO / USB1_XO - optional USB PHY reference clock.
• CPTS_REFCLK_P / CPTS_REFCLK_N - CPTS reference clock LVDS differential input.

Figure 5-8 shows the external input clock sources to peripherals.

Figure 5-8 Input Clocks Interface

For more information related to clock inputs, see section Clock Management in chapter Device Configuration of the Device TRM.