ZHCSBT2G November   2012  – October 2017 66AK2H06 , 66AK2H12 , 66AK2H14

PRODUCTION DATA.  

  1. 1 器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
      1. 1.3.1 KeyStone II 的增强功能
    4. 1.4 功能方框图
  2. 2 修订历史记录
  3. 3 Device Comparison
    1. 3.1 Related Products
  4. 4 Terminal Configuration and Functions
    1. 4.1 Package Terminals
    2. 4.2 Pin Map
    3. 4.3 Terminal Functions
    4. 4.4 Pullup/Pulldown Resistors
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Power Consumption Summary
    5. 5.5 Electrical Characteristics
    6. 5.6 Thermal Resistance Characteristics for PBGA Package [AAW]
    7. 5.7 Power Supply to Peripheral I/O Mapping
  6. 6 C66x CorePac
    1. 6.1 C66x DSP CorePac
    2. 6.2 Memory Architecture
      1. 6.2.1 L1P Memory
      2. 6.2.2 L1D Memory
      3. 6.2.3 L2 Memory
      4. 6.2.4 Multicore Shared Memory SRAM
      5. 6.2.5 L3 Memory
    3. 6.3 Memory Protection
    4. 6.4 Bandwidth Management
    5. 6.5 Power-Down Control
    6. 6.6 C66x CorePac Revision
      1. Table 6-2 CorePac Revision ID Register (MM_REVID) Field Descriptions
    7. 6.7 C66x CorePac Register Descriptions
  7. 7 ARM CorePac
    1. 7.1 Features
    2. 7.2 System Integration
    3. 7.3 ARM Cortex-A15 Processor
      1. 7.3.1 Overview
      2. 7.3.2 Features
      3. 7.3.3 ARM Interrupt Controller
      4. 7.3.4 Endianess
    4. 7.4 CFG Connection
    5. 7.5 Main TeraNet Connection
    6. 7.6 Clocking and Reset
      1. 7.6.1 Clocking
      2. 7.6.2 Reset
  8. 8 Memory, Interrupts, and EDMA for 66AK2Hxx
    1. 8.1 Memory Map Summary for 66AK2Hxx
    2. 8.2 Memory Protection Unit (MPU) for 66AK2Hxx
      1. 8.2.1 MPU Registers
        1. 8.2.1.1 MPU Register Map
        2. 8.2.1.2 Device-Specific MPU Registers
          1. 8.2.1.2.1 Configuration Register (CONFIG)
            1. Table 8-9 Configuration Register Field Descriptions
      2. 8.2.2 MPU Programmable Range Registers
        1. 8.2.2.1 Programmable Range n Start Address Register (PROGn_MPSAR)
          1. Table 8-10 Programmable Range n Start Address Register Field Descriptions
        2. 8.2.2.2 Programmable Range n - End Address Register (PROGn_MPEAR)
          1. Table 8-14 Programmable Range n End Address Register Field Descriptions
        3. 8.2.2.3 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPAR)
          1. Table 8-18 Programmable Range n Memory Protection Page Attribute Register Field Descriptions
    3. 8.3 Interrupts for 66AK2Hxx
      1. 8.3.1 Interrupt Sources and Interrupt Controller
      2. 8.3.2 CIC Registers
        1. 8.3.2.1 CIC0 Register Map
        2. 8.3.2.2 CIC1 Register Map
        3. 8.3.2.3 CIC2 Register Map
      3. 8.3.3 Inter-Processor Register Map
      4. 8.3.4 NMI and LRESET
    4. 8.4 Enhanced Direct Memory Access (EDMA3) Controller for 66AK2Hxx
      1. 8.4.1 EDMA3 Device-Specific Information
      2. 8.4.2 EDMA3 Channel Controller Configuration
      3. 8.4.3 EDMA3 Transfer Controller Configuration
      4. 8.4.4 EDMA3 Channel Synchronization Events
  9. 9 System Interconnect
    1. 9.1 Internal Buses and Switch Fabrics
    2. 9.2 Switch Fabric Connections Matrix - Data Space
    3. 9.3 TeraNet Switch Fabric Connections Matrix - Configuration Space
    4. 9.4 Bus Priorities
  10. 10Device Boot and Configuration
    1. 10.1 Device Boot
      1. 10.1.1 Boot Sequence
      2. 10.1.2 Boot Modes Supported
        1. 10.1.2.1 Boot Device Field
          1. Table 10-3 Boot Mode Pins: Boot Device Values
        2. 10.1.2.2 Device Configuration Field
          1. 10.1.2.2.1 Sleep Boot Mode Configuration
            1. Table 10-4 Sleep Boot Configuration Field Descriptions
          2. 10.1.2.2.2 I2C Boot Device Configuration
            1. 10.1.2.2.2.1 I2C Passive Mode
              1. Table 10-5 I2C Passive Mode Device Configuration Field Descriptions
            2. 10.1.2.2.2.2 I2C Master Mode
              1. Table 10-6 I2C Master Mode Device Configuration Field Descriptions
          3. 10.1.2.2.3 SPI Boot Device Configuration
            1. Table 10-7 SPI Device Configuration Field Descriptions
          4. 10.1.2.2.4 EMIF Boot Device Configuration
            1. Table 10-8 EMIF Boot Device Configuration Field Descriptions
          5. 10.1.2.2.5 NAND Boot Device Configuration
            1. Table 10-9 NAND Boot Device Configuration Field Descriptions
        3. 10.1.2.3 Serial Rapid I/O Boot Device Configuration
          1. Table 10-10 Serial Rapid I/O Boot Device Configuration Field Descriptions
        4. 10.1.2.4 Ethernet (SGMII) Boot Device Configuration
          1. Table 10-11 Ethernet (SGMII) Boot Device Configuration Field Descriptions
          2. 10.1.2.4.1   PCIe Boot Device Configuration
            1. Table 10-12 PCIe Boot Device Configuration Field Descriptions
          3. 10.1.2.4.2   HyperLink Boot Device Configuration
            1. Table 10-14 HyperLink Boot Device Configuration Field Descriptions
          4. 10.1.2.4.3   UART Boot Device Configuration
            1. Table 10-15 UART Boot Configuration Field Descriptions
        5. 10.1.2.5 Boot Parameter Table
          1. 10.1.2.5.1  EMIF16 Boot Parameter Table
          2. 10.1.2.5.2  SRIO Boot Parameter Table
          3. 10.1.2.5.3  Ethernet Boot Parameter Table
          4. 10.1.2.5.4  PCIe Boot Parameter Table
          5. 10.1.2.5.5  I2C Boot Parameter Table
          6. 10.1.2.5.6  SPI Boot Parameter Table
          7. 10.1.2.5.7  HyperLink Boot Parameter Table
          8. 10.1.2.5.8  UART Boot Parameter Table
          9. 10.1.2.5.9  NAND Boot Parameter Table
          10. 10.1.2.5.10 DDR3 Configuration Table
        6. 10.1.2.6 Second-Level Bootloaders
      3. 10.1.3 SoC Security
      4. 10.1.4 System PLL Settings
        1. 10.1.4.1 ARM CorePac System PLL Settings
    2. 10.2 Device Configuration
      1. 10.2.1 Device Configuration at Device Reset
      2. 10.2.2 Peripheral Selection After Device Reset
      3. 10.2.3 Device State Control Registers
        1. 10.2.3.1  Device Status (DEVSTAT) Register
          1. Table 10-31 Device Status Register Field Descriptions
        2. 10.2.3.2  Device Configuration Register
          1. Table 10-32 Device Configuration Register Field Descriptions
        3. 10.2.3.3  JTAG ID (JTAGID) Register Description
          1. Table 10-33 JTAG ID Register Field Descriptions
        4. 10.2.3.4  Kicker Mechanism (KICK0 and KICK1) Register
        5. 10.2.3.5  DSP Boot Address Register (DSP_BOOT_ADDRn)
          1. Table 10-1 DSP BOOT Address Register (DSP_BOOT_ADDRn)
        6. 10.2.3.6  LRESETNMI PIN Status (LRSTNMIPINSTAT) Register
          1. Table 10-35 LRESETNMI PIN Status Register Field Descriptions
        7. 10.2.3.7  LRESETNMI PIN Status Clear (LRSTNMIPINSTAT_CLR) Register
          1. Table 10-36 LRESETNMI PIN Status Clear Register Field Descriptions
        8. 10.2.3.8  Reset Status (RESET_STAT) Register
          1. Table 10-37 Reset Status Register Field Descriptions
        9. 10.2.3.9  Reset Status Clear (RESET_STAT_CLR) Register
          1. Table 10-38 Reset Status Clear Register Field Descriptions
        10. 10.2.3.10 Boot Complete (BOOTCOMPLETE) Register
          1. Table 10-39 Boot Complete Register Field Descriptions
        11. 10.2.3.11 Power State Control (PWRSTATECTL) Register
          1. Table 10-40 Power State Control Register Field Descriptions
        12. 10.2.3.12 NMI Event Generation to C66x CorePac (NMIGRx) Register
          1. Table 10-41 NMI Generation Register Field Descriptions
        13. 10.2.3.13 IPC Generation (IPCGRx) Registers
          1. Table 10-42 IPC Generation Registers Field Descriptions
        14. 10.2.3.14 IPC Acknowledgment (IPCARx) Registers
          1. Table 10-43 IPC Acknowledgment Registers Field Descriptions
        15. 10.2.3.15 IPC Generation Host (IPCGRH) Register
          1. Table 10-44 IPC Generation Registers Field Descriptions
        16. 10.2.3.16 IPC Acknowledgment Host (IPCARH) Register
          1. Table 10-45 IPC Acknowledgment Register Field Descriptions
        17. 10.2.3.17 Timer Input Selection Register (TINPSEL)
          1. Table 10-46 Timer Input Selection Field Description
        18. 10.2.3.18 Timer Output Selection Register (TOUTPSEL)
          1. Table 10-47 Timer Output Selection Register Field Descriptions
        19. 10.2.3.19 Reset Mux (RSTMUXx) Register
          1. Table 10-48 Reset Mux Register Field Descriptions
        20. 10.2.3.20 Device Speed (DEVSPEED) Register
          1. Table 10-49 Device Speed Register Field Descriptions
        21. 10.2.3.21 ARM Endian Configuration Register 0 (ARMENDIAN_CFGr_0), r=0..7
          1. Table 10-50 ARM Endian Configuration Register 0 Field Descriptions
        22. 10.2.3.22 ARM Endian Configuration Register 1 (ARMENDIAN_CFGr_1), r=0..7
          1. Table 10-51 ARM Endian Configuration Register 1 Field Descriptions
        23. 10.2.3.23 ARM Endian Configuration Register 2 (ARMENDIAN_CFGr_2), r=0..7
          1. Table 10-52 ARM Endian Configuration Register 2 Field Descriptions
        24. 10.2.3.24 Chip Miscellaneous Control (CHIP_MISC_CTL0) Register
          1. Table 10-53 Chip Miscellaneous Control Register Field Descriptions
        25. 10.2.3.25 Chip Miscellaneous Control (CHIP_MISC_CTL1) Register
          1. Table 10-54 Chip Miscellaneous Control Register Field Descriptions
        26. 10.2.3.26 System Endian Status Register (SYSENDSTAT)
          1. Table 10-55 System Endian Status Register Field Descriptions
        27. 10.2.3.27 SYNECLK_PINCTL Register
          1. Table 10-56 SYNECLK_PINCTL Register Field Descriptions
        28. 10.2.3.28 USB PHY Control (USB_PHY_CTLx) Registers
          1. Table 10-57 USB_PHY_CTL0 Register Field Descriptions
          2. Table 10-58 USB_PHY_CTL1 Register Field Descriptions
          3. Table 10-59 USB_PHY_CTL2 Register Field Descriptions
          4. Table 10-60 USB_PHY_CTL3 Register Field Descriptions
          5. Table 10-61 USB_PHY_CTL4 Register Field Descriptions
          6. Table 10-62 USB_PHY_CTL5 Register Field Descriptions
  11. 1166AK2Hxx Peripheral Information
    1. 11.1  Recommended Clock and Control Signal Transition Behavior
    2. 11.2  Power Supplies
      1. 11.2.1 Power-Up Sequencing
        1. 11.2.1.1 Core-Before-IO Power Sequencing
        2. 11.2.1.2 IO-Before-Core Power Sequencing
        3. 11.2.1.3 Prolonged Resets
        4. 11.2.1.4 Clocking During Power Sequencing
      2. 11.2.2 Power-Down Sequence
      3. 11.2.3 Power Supply Decoupling and Bulk Capacitor
      4. 11.2.4 SmartReflex
        1. Table 11-5 SmartReflex 4-Pin 6-bit VID Interface Switching Characteristics
    3. 11.3  Power Sleep Controller (PSC)
      1. 11.3.1 Power Domains
      2. 11.3.2 Clock Domains
      3. 11.3.3 PSC Register Memory Map
    4. 11.4  Reset Controller
      1. 11.4.1 Power-on Reset
      2. 11.4.2 Hard Reset
      3. 11.4.3 Soft Reset
      4. 11.4.4 Local Reset
      5. 11.4.5 ARM CorePac Reset
      6. 11.4.6 Reset Priority
      7. 11.4.7 Reset Controller Register
      8. 11.4.8 Reset Electrical Data and Timing
        1. Table 11-10 Reset Timing Requirements
        2. Table 11-11 Reset Switching Characteristics
        3. Table 11-12 Boot Configuration Timing Requirements
    5. 11.5  Main PLL, ARM PLL, DDR3A PLL, DDR3B PLL, PASS PLL and the PLL Controllers
      1. 11.5.1 Main PLL Controller Device-Specific Information
        1. 11.5.1.1 Internal Clocks and Maximum Operating Frequencies
        2. 11.5.1.2 Local Clock Dividers
        3. 11.5.1.3 Module Clock Input
        4. 11.5.1.4 Main PLL Controller Operating Modes
        5. 11.5.1.5 Main PLL Stabilization, Lock, and Reset Times
      2. 11.5.2 PLL Controller Memory Map
        1. 11.5.2.1 PLL Secondary Control Register (SECCTL)
          1. Table 11-16 PLL Secondary Control Register Field Descriptions
        2. 11.5.2.2 PLL Controller Divider Register (PLLDIV3 and PLLDIV4)
          1. Table 11-17 PLL Controller Divider Register Field Descriptions
        3. 11.5.2.3 PLL Controller Clock Align Control Register (ALNCTL)
          1. Table 11-18 PLL Controller Clock Align Control Register Field Descriptions
        4. 11.5.2.4 PLLDIV Divider Ratio Change Status Register (DCHANGE)
          1. Table 11-19 PLLDIV Divider Ratio Change Status Register Field Descriptions
        5. 11.5.2.5 SYSCLK Status Register (SYSTAT)
          1. Table 11-20 SYSCLK Status Register Field Descriptions
        6. 11.5.2.6 Reset Type Status Register (RSTYPE)
          1. Table 11-21 Reset Type Status Register Field Descriptions
        7. 11.5.2.7 Reset Control Register (RSTCTRL)
          1. Table 11-22 Reset Control Register Field Descriptions
        8. 11.5.2.8 Reset Configuration Register (RSTCFG)
          1. Table 11-23 Reset Configuration Register Field Descriptions
        9. 11.5.2.9 Reset Isolation Register (RSISO)
          1. Table 11-24 Reset Isolation Register Field Descriptions
      3. 11.5.3 Main PLL Control Registers
        1. Table 11-25 Main PLL Control Register 0 (MAINPLLCTL0) Field Descriptions
        2. Table 11-26 Main PLL Control Register 1 (MAINPLLCTL1) Field Descriptions
      4. 11.5.4 ARM PLL Control Registers
        1. Table 11-27 ARM PLL Control Register 0 Field Descriptions
        2. Table 11-28 ARM PLL Control Register 1 Field Descriptions
      5. 11.5.5 Main PLL Controller, ARM, SRIO, HyperLink, PCIe, USB Clock Input Electrical Data and Timing
        1. Table 11-29 Main PLL Controller, ARM, SRIO, HyperLink, PCIe, USB Clock Input Timing Requirements
    6. 11.6  DDR3A PLL and DDR3B PLL
      1. 11.6.1 DDR3A PLL and DDR3B PLL Control Registers
        1. Table 11-30 DDR3A PLL and DDR3B PLL Control Register 0 Field Descriptions
        2. Table 11-31 DDR3A PLL and DDR3B PLL Control Register 1 Field Descriptions
      2. 11.6.2 DDR3A PLL and DDR3B PLL Device-Specific Information
      3. 11.6.3 DDR3 PLL Input Clock Electrical Data and Timing
        1. Table 11-32 DDR3 PLL DDRCLK(N|P) Timing Requirements
    7. 11.7  PASS PLL
      1. 11.7.1 PASS PLL Local Clock Dividers
      2. 11.7.2 PASS PLL Control Registers
        1. Table 11-33 PASS PLL Control Register 0 Field Descriptions (PASSPLLCTL0)
        2. Table 11-34 PASS PLL Control Register 1 Field Descriptions (PASSPLLCTL1)
      3. 11.7.3 PASS PLL Device-Specific Information
      4. 11.7.4 PASS PLL Input Clock Electrical Data and Timing
        1. Table 11-35 PASS PLL Timing Requirements
    8. 11.8  External Interrupts
      1. 11.8.1 External Interrupts Electrical Data and Timing
        1. Table 11-36 NMI and LRESET Timing Requirements
    9. 11.9  DDR3A and DDR3B Memory Controllers
      1. 11.9.1 DDR3 Memory Controller Device-Specific Information
      2. 11.9.2 DDR3 Slew Rate Control
      3. 11.9.3 DDR3 Memory Controller Electrical Data and Timing
    10. 11.10 I2C Peripheral
      1. 11.10.1 I2C Device-Specific Information
      2. 11.10.2 I2C Peripheral Register Description
      3. 11.10.3 I2C Electrical Data and Timing
        1. Table 11-38 I2C Timing Requirements
        2. Table 11-39 I2C Switching Characteristics
    11. 11.11 SPI Peripheral
      1. 11.11.1 SPI Electrical Data and Timing
        1. Table 11-40 SPI Timing Requirements
        2. Table 11-41 SPI Switching Characteristics
    12. 11.12 HyperLink Peripheral
      1. Table 11-42 HyperLink Peripheral Timing Requirements
      2. Table 11-43 HyperLink Peripheral Switching Characteristics
    13. 11.13 UART Peripheral
      1. Table 11-44 UART Timing Requirements
      2. Table 11-45 UART Switching Characteristics
    14. 11.14 PCIe Peripheral
    15. 11.15 Packet Accelerator
    16. 11.16 Security Accelerator
    17. 11.17 Network Coprocessor Gigabit Ethernet (GbE) Switch Subsystem
      1. Table 11-46 MACID1 Register Field Descriptions
      2. Table 11-47 MACID2 Register Field Descriptions
      3. Table 11-48 RFTCLK Select Register Field Descriptions
    18. 11.18 SGMII and XFI Management Data Input/Output (MDIO)
      1. Table 11-49 MDIO Timing Requirements
      2. Table 11-50 MDIO Switching Characteristics
    19. 11.19 Ten-Gigabit Ethernet (10GbE) Switch Subsystem
      1. 11.19.1 10GbE Supported Features
    20. 11.20 Timers
      1. 11.20.1 Timers Device-Specific Information
      2. 11.20.2 Timers Electrical Data and Timing
        1. Table 11-51 Timer Input Timing Requirements
        2. Table 11-52 Timer Output Switching Characteristics
    21. 11.21 Serial RapidIO (SRIO) Port
      1. 11.21.1 Serial RapidIO Device-Specific Information
    22. 11.22 General-Purpose Input/Output (GPIO)
      1. 11.22.1 GPIO Device-Specific Information
      2. 11.22.2 GPIO Peripheral Register Description
      3. 11.22.3 GPIO Electrical Data and Timing
        1. Table 11-54 GPIO Input Timing Requirements
        2. Table 11-55 GPIO Output Switching Characteristics
    23. 11.23 Semaphore2
    24. 11.24 Universal Serial Bus 3.0 (USB 3.0)
    25. 11.25 EMIF16 Peripheral
      1. 11.25.1 EMIF16 Electrical Data and Timing
        1. Table 11-56 EMIF16 Asynchronous Memory Timing Requirements
    26. 11.26 Emulation Features and Capability
      1. 11.26.1 Chip-Level Features
        1. 11.26.1.1 ARM Subsystem Features
        2. 11.26.1.2 DSP Features
      2. 11.26.2 ICEPick Module
        1. 11.26.2.1 ICEPick Dynamic Tap Insertion
    27. 11.27 Debug Port (EMUx)
      1. 11.27.1 Concurrent Use of Debug Port
      2. 11.27.2 Master ID for Hardware and Software Messages
      3. 11.27.3 SoC Cross-Triggering Connection
      4. 11.27.4 Peripherals-Related Debug Requirement
      5. 11.27.5 Advanced Event Triggering (AET)
      6. 11.27.6 Trace
        1. 11.27.6.1 Trace Electrical Data and Timing
          1. Table 11-66 Trace Switching Characteristics
      7. 11.27.7 IEEE 1149.1 JTAG
        1. 11.27.7.1 IEEE 1149.1 JTAG Compatibility Statement
        2. 11.27.7.2 JTAG Electrical Data and Timing
          1. Table 11-67 JTAG Test Port Timing Requirements
          2. Table 11-68 JTAG Test Port Switching Characteristics
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Tools and Software
    3. 12.3 Documentation Support
    4. 12.4 Related Links
    5. 12.5 Community Resources
    6. 12.6 商标
    7. 12.7 静电放电警告
    8. 12.8 术语表
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Packaging Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • AAW|1517
散热焊盘机械数据 (封装 | 引脚)
订购信息

10.2.3.28 USB PHY Control (USB_PHY_CTLx) Registers

The USB PHY Control (USB_PHY_CTLx) registers are shown in Figure 10-38, Figure 10-39, Figure 10-40, Figure 10-41, Figure 10-42, and Figure 10-43 and described in Table 10-57, Table 10-58, Table 10-59, Table 10-60, Figure 10-42, and Table 10-62.

Figure 10-38 USB_PHY_CTL0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
R-0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved PHY_
RTUNE_
ACK		 PHY_
RTUNE_
REQ		 Rsvd PHY_TC_
VATESTENB		 PHY_TC_TEST_
POWER
DOWN_
SSP		 PHY_TC_TEST_
POWER
DOWN_
HSP		 PHY_TC_LOOP
BACKENB		 Rsvd UTMI_
VBUS
VLDEXT		 UTMI_TXBITSTUFFENH UTMI_TXBITSTUFFEN
R-0 R-0 R/W-0 R-0 R/W-00 R/W-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0
Legend: R = Read only; W = Write only; -n = value after reset

Table 10-57 USB_PHY_CTL0 Register Field Descriptions

Bit Field Description
31-12 Reserved Reserved
11 PHY_RTUNE_ACK The PHY uses an external resistor to calibrate the termination impedances of the PHY's high-speed inputs and outputs.

The resistor is shared between the USB2.0 high-speed outputs and the Super-speed I/O. Each time the PHY is taken out of a reset, a termination calibration is performed. For SS link, the calibration can also be requested externally by asserting the PHY_RTUNE_REQ. When the calibration is complete, the PHY_RTUNE_ACK transitions low.

A resistor calibration on the SS link cannot be performed while the link is operational

10 PHY_RTUNE_REQ See PHY_RTUNE_ACK.
9 Reserved Reserved
8-7 PHY_TC_VATESTENB Analog Test Pin Select.

Enables analog test voltages to be placed on the ID pin.

  • 11 = Invalid setting.
  • 10 = Invalid setting.
  • 01 = Analog test voltages can be viewed or applied on ID.
  • 00 = Analog test voltages cannot be viewed or applied on ID.
6 PHY_TC_TEST_POWERDOWN_SSP SS Function Circuits Power-Down Control.

Powers down all SS function circuitry in the PHY for IDDQ testing.

5 PHY_TC_TEST_POWERDOWN_HSP HS Function Circuits Power-Down Control

Powers down all HS function circuitry in the PHY for IDDQ testing.

4 PHY_TC_LOOPBACKENB Loop-back Test Enable

Places the USB3.0 PHY in HS Loop-back mode, which concurrently enables the HS receive and transmit logic.

  • 1 = During HS data transmission, the HS receive logic is enabled.
  • 0 = During HS data transmission, the HS receive logic is disabled.
3 Reserved
  • Reserved
2 UTMI_VBUSVLDEXT External VBUS Valid Indicator

Function: Valid in Device mode and only when the VBUSVLDEXTSEL signal is set to 1'b1. VBUSVLDEXT indicates whether the VBUS signal on the USB cable is valid. In addition, VBUSVLDEXT enables the pull-up resistor on the D+ line.

  • 1 = VBUS signal is valid, and the pull-up resistor on D+ is enabled.
  • 0 = VBUS signal is not valid, and the pull-up resistor on D+ is disabled.
1 UTMI_TXBITSTUFFENH High-byte Transmit Bit-Stuffing Enable

Function: controls bit stuffing on DATAINH[7:0] when OPMODE[1:0]=11b.

  • 1 = Bit stuffing is enabled.
  • 0 = Bit stuffing is disabled.
0 UTMI_TXBITSTUFFEN Low-byte Transmit Bit-Stuffing Enable

Function: controls bit stuffing on DATAIN[7:0] when OPMODE[1:0]=11b.

  • 1 = Bit stuffing is enabled.
  • 0 = Bit stuffing is disabled.
Figure 10-39 USB_PHY_CTL1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
R-0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved PIPE_REF_CLKREQ_N PIPE_TX2RX_LOOPBK PIPE_EXT_PCLK_
REQ		 PIPE_ALT_CLK_
SEL		 PIPE_ALT_CLK_
REQ		 PIPE_ALT_CLK_EN
R-0 R-0 R/W-0 R/W-0 R/W-0 R-0 R/W-0
Legend: R = Read only; R/W = Read/Write, -n = value after reset

Table 10-58 USB_PHY_CTL1 Register Field Descriptions

Bit Field Description
31-6 Reserved Reserved
5 PIPE_REF_CLKREQ_N Reference Clock Removal Acknowledge.

When the pipeP_power-down control into the PHY turns off the MPLL in the P3 state, PIPE_REF_CLKREQ_N is asserted after the PLL is stable and the reference clock can be removed.

4 PIPE_TX2RX_LOOPBK Loop-back.

When this signal is asserted, data from the transmit predriver is looped back to the receiver slicers. LOS is bypassed and based on the tx_en input so that rx_los=!tx_data_en.

3 PIPE_EXT_PCLK_REQ External PIPE Clock Enable Request.

When asserted, this signal enables the pipeP_pclk output regardless of power state (along with the associated increase in power consumption).

2 PIPE_ALT_CLK_SEL Alternate Clock Source Select.

Selects the alternate clock sources instead of the internal MPLL outputs for the PCS clocks.

  • 1 = Uses alternate clocks.
  • 0 = Users internal MPLL clocks.

Change only during a reset.

1 PIPE_ALT_CLK_REQ Alternate Clock Source Request.

Indicates that the alternate clocks are needed by the slave PCS (that is, to boot the master MPLL). Connect to the alt_clk_en on the master.

0 PIPE_ALT_CLK_EN Alternate Clock Enable.

Enables the ref_pcs_clk and ref_pipe_pclk output clocks (if necessary, powers up the MPLL).

Figure 10-40 USB_PHY_CTL2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved PHY_PC_LOS_BIAS PHY_PC_TXVREFTUNE PHY_PC_
TXRISETUNE		 PHY_PC_
TXRESTUNE		 PHY_PC_
TX
PREEMP
PULSE
T
UNE		 PHY_PC_TXPREEMPAMPTUNE
R-0 R/W-101 R/W-1000 R/W-01 R/W-01 R/W-0 R/W-00
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PHY_PC_
TXHSXVTUNE		 PHY_PC_TXFSLSTUNE PHY_PC_SQRXTUNE PHY_PC_OTGTUNE Rsvd PHY_PC_
COMPDISTUNE
R/W-11 R/W-0011 R/W-011 R/W-100 R-0 R/W-100
Legend: R = Read only; R/W = Read/Write, -n = value after reset

Table 10-59 USB_PHY_CTL2 Register Field Descriptions

Bit Field Description
31-30 Reserved Reserved
29-27 PHY_PC_LOS_BIAS Loss-of-Signal Detector Threshold Level Control.

Sets the LOS detection threshold level.

  • +1 = results in a +15 mVp incremental change in the LOS threshold.
  • –1 = results in a –15 mVp incremental change in the LOS threshold.

Note: the 000b setting is reserved and must not be used.

26-23 PHY_PC_TXVREFTUNE HS DC Voltage Level Adjustment.

Adjusts the high-speed DC level voltage.

  • +1 = results in a +1.25% incremental change in high-speed DC voltage level.
  • –1 = results in a –1.25% incremental change in high-speed DC voltage level.
22-21 PHY_PC_TXRISETUNE HS Transmitter Rise/Fall TIme Adjustment.

Adjusts the rise/fall times of the high-speed waveform.

  • +1 = results in a –4% incremental change in the HS rise/fall time.
  • –1 = results in a +4% incremental change in the HS rise/fall time.
20-19 PHY_PC_TXRESTUNE USB Source Impedance Adjustment.

Some applications require additional devices to be added on the USB, such as a series switch, which can add significant series resistance. This bus adjusts the driver source impedance to compensate for added series resistance on the USB.

18 PHY_PC_
TXPREEMPPULSETUNE		 HS Transmitter Pre-Emphasis Duration Control.

Controls the duration for which the HS pre-emphasis current is sourced onto DP or DM. It is defined in terms of unit amounts. One unit of pre-emphasis duration is approximately 580 ps and is defined as 1x pre-emphasis duration. This signal valid only if either txpreempamptune[1] or txpreempamptune[0] is set to 1.

  • 1 = 1x, short pre-emphasis current duration.
  • 0 = 2x, long pre-emphasis current duration.
17-16 PHY_PC_TXPREEMPAMPTUNE HS Transmitter Pre-Emphasis Current Control.

Controls the amount of current sourced to DP and DM after a J-to-K or K-to-J transition.

The HS Transmitter pre-emphasis current is defined in terms of unit amounts. One unit amount is approximately 600 µA and is defined as 1x pre-emphasis current.

  • 11 = 3x pre-emphasis current.
  • 10 = 2x pre-emphasis current.
  • 01 = 1x pre-emphasis current.
  • 00 = HS Transmitter pre-emphasis is disabled.
15-14 PHY_PC_TXHSXVTUNE Transmitter High-Speed Crossover Adjustment.

Adjusts the voltage at which the DP and DM signals cross while transmitting in HS mode.

  • 11 = Default setting.
  • 10 = +15 mV
  • 01 = –15 mV
  • 00 = Reserved
13-10 PHY_PC_TXFSLSTUNE FS/LS Source Impedance Adjustment.

Adjusts the low- and full-speed single-ended source impedance while driving high.

This parameter control is encoded in thermometer code.

  • +1 = results in a –2.5% incremental change in threshold voltage level.
  • –1 = results in a +2.5% incremental change in threshold voltage level.

Any nonthermometer code setting (that is 1001) is not supported and reserved.

9-7 PHY_PC_SQRXTUNE Squelch Threshold Adjustment.

Adjusts the voltage level for the threshold used to detect valid high-speed data.

  • +1 = results in a –5% incremental change in threshold voltage level.
  • –1 = results in a +5% incremental change in threshold voltage level.
6-4 PHY_PC_OTGTUNE VBUS Valid Threshold Adjustment.

Adjusts the voltage level for the VBUS valid threshold.

  • +1 = results in a +1.5% incremental change in threshold voltage level.
  • –1 = results in a –1.5% incremental change in threshold voltage level.
3 Reserved Reserved
2-0 PHY_PC_COMPDISTUNE Disconnect Threshold Adjustment.

Adjusts the voltage level for the threshold used to detect a disconnect event at the host.

  • +1 = results in a +1.5% incremental change in the threshold voltage level.
  • –1 = results in a –1.5% incremental change in the threshold voltage level.
Figure 10-41 USB_PHY_CTL3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved PHY_PC_PCS_TX_SWING_FULL PHY_PC_PCS_TX_DEEMPH_6DB Rsvd
R-0 R/W-1111000 R/W-100000 R-0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved PHY_PC_PCS_TX_DEEMPH_3P5DB PHY_PC_LOS_LEVEL
R-0 R/W-010101 R/W-01001
Legend: R = Read only; R/W = Read/Write, -n = value after reset

Table 10-60 USB_PHY_CTL3 Register Field Descriptions

Bit Field Description
31-30 Reserved Reserved
29-23 PHY_PC_PCS_TX_SWING_
FULL		 Tx Amplitude (Full Swing Mode).

Sets the launch amplitude of the transmitter. It can be used to tune Rx eye for compliance.

22-17 PHY_PC_PCS_TX_DEEMPH_
6DB		 Tx De-Emphasis at 6 dB.

Sets the Tx driver de-emphasis value when pipeP_tx_deemph[1:0] is set to 10b (according to the PIPE3 specification). This bus is provided for completeness and as a second potential launch amplitude.

16-11 Reserved Reserved
10-5 PHY_PC_PCS_TX_DEEMPH_
3P5DB		 Tx De-Emphasis at 3.5 dB.

Sets the Tx driver de-emphasis value when pipeP_tx_deemph[1:0] is set to 10b (according to the PIPE3 specification). Can be used for Rx eye compliance.

4-0 PHY_PC_LOS_LEVEL Loss-of-Signal Detector Sensitivity Level Control.

Sets the LOS detection threshold level. This signal must be set to 0x9.

Figure 10-42 USB_PHY_CTL4 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PHY_SSC_EN PHY_REF_USE_
PAD		 PHY_REF_SSP_EN PHY_
MPLL_
REFSSC_
CLK_EN		 PHY_FSEL PHY_RETENABLEN PHY_REFCLKSEL PHY_
COMMON
ONN		 Rsvd PHY_OTG_VBUSVLDEXTSEL
R/W-1 R/W-0 R/W-0 R/W-0 R/W-100111 R/W-1 R/W-10 R/W-0 R-0 R/W-0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PHY_OTG
_ OTG
DISABLE		 PHY_PC_TX_VBOOST_LVL PHY_PC_LANE0_TX_TERM_
OFFSET		 Reserved
R/W-1 R/W-100 R/W-00000 R-0
Legend: R = Read only; R/W = Read/Write, -n = value after reset

Table 10-61 USB_PHY_CTL4 Register Field Descriptions

Bit Field Description
31 PHY_SSC_EN Spread Spectrum Enable.

Enables spread spectrum clock production (0.5% down-spread at ~31.5 KHz) in the USB3.0 PHY. If the reference clock already has spread spectrum applied, ssc_en must be deasserted.

30 PHY_REF_USE_PAD Select Reference Clock Connected to ref_pad_clk_{p,m}.

When asserted, selects the external ref_pad_clk_{p,m} inputs as the reference clock source. When deasserted, ref_alt_clk_{p,m} are selected for an on-chip reference clock source.

29 PHY_REF_SSP_EN Reference Clock Enables for SS function.

Enables the reference clock to the prescaler. The ref_ssp_en signal must remain deasserted until the reference clock is running at the appropriate frequency, at which point ref_ssp_en can be asserted. For lower power states, ref_ssp_en can also be de asserted.

28 PHY_MPLL_REFSSC_CLK_EN Double-Word Clock Enable.

Enables/disables the mpll_refssc_clk signal. To prevent clock glitch, it must be changed when the PHY is inactive.

27-22 PHY_FSEL Frequency Selection.

Selects the reference clock frequency used for both SS and HS operations. The value for fsel combined with the other clock and enable signals will determine the clock frequency used for SS and HS operations and if a shared or separate reference clock will be used.

21 PHY_RETENABLEN Lowered Digital Supply Indicator.

Indicates that the vp digital power supply has been lowered in Suspend mode. This signal must be deasserted before the digital power supply is lowered.

  • 1 = Normal operating mode.
  • 0 = The analog blocks are powered down.
20-19 PHY_REFCLKSEL Reference Clock Select for PLL Block.

Selects reference clock source for the HS PLL block.

  • 11 = HS PLL uses EXTREFCLK as reference.
  • 10 = HS PLL uses either ref_pad_clk_{p,m} or ref_alt_clk_{p,m} as reference.
  • x0 = Reserved.
18 PHY_COMMONONN Common Block Power-Down Control.

Controls the power-down signals in the HS Bias and PLL blocks when the USB3.0 PHY is in Suspend or Sleep mode.

  • 1 = In Suspend or Sleep mode, the HS Bias and PLL blocks are powered down.
  • 0 = In Suspend or Sleep mode, the HS Bias and PLL blocks remain powered and continue to draw current.
17 Reserved Reserved
16 PHY_OTG_VBUSVLDEXTSEL External VBUS Valid Select.

Selects the VBUSVLDEXT input or the internal Session Valid comparator to indicate when the VBUS signal on the USB cable is valid.

  • 1 = VBUSVLDEXT input is used.
  • 0 = Internal Session Valid comparator is used.
15 PHY_OTG_OTGDISABLE OTG Block Disable.

Powers down the OTG block, which disables the VBUS Valid and Session End comparators. The Session Valid comparator (the output of which is used to enable the pull-up resistor on DP in Device mode) is always on irrespective of the state of otgdisable. If the application does not use the OTG function, setting this signal to high to save power.

  • 1 = OTG block is powered down.
  • 0 = OTG block is powered up.
14-12 PHY_PC_TX_VBOOST_LVL Tx Voltage Boost Level.

Sets the boosted transmit launch amplitude (mVppd).

The default setting is intended to set the launch amplitude to approximately 1,008mVppd.

  • +1 = results in a +156 mVppd change in the Tx launch amplitude.
  • –1 = results in a –156 mVppd change in the Tx launch amplitude.
11-7 PHY_PC_LANE0_TX_TERM_
OFFSET		 Transmitter Termination Offset.

Enables adjusting the transmitter termination value from the default value of 60 Ω.

6-0 Reserved Reserved
Figure 10-43 USB_PHY_CTL5 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved PHY_REF_CLKDIV2 PHY_MPLL_MULTIPLIER[6:0]
R-0 R/W-0 R/W +0011001
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PHY_MPLL_MULTIPLIER[6:0] PHY_SSC_REF_CLK_SEL Rsvd PHY_SSC_RANGE
R/W +0011001 R/W-000000000 R-0 R/W-000
Legend: R = Read only; R/W = Read/Write, -n = value after reset

Table 10-62 USB_PHY_CTL5 Register Field Descriptions

Bit Field Description
31-21 Reserved Reserved
20 PHY_REF_CLKDIV2 Input Reference Clock Divider Control.

If the input reference clock frequency is greater than 100 MHz, this signal must be asserted. The reference clock frequency is then divided by 2 to keep it in the range required by the MPLL.

When this input is asserted, the ref_ana_usb2_clk (if used) frequency will be the reference clock frequency divided by 4.

19-13 PHY_MPLL_MULTIPLIER[6:0] MPLL Frequency Multiplier Control.

Multiplies the reference clock to a frequency suitable for intended operating speed.

12-4 PHY_SSC_REF_CLK_SEL Spread Spectrum Reference Clock Shifting.

Enables nonstandard oscillator frequencies to generate targeted MPLL output rates. Input corresponds to frequency-synthesis coefficient.

  • . ssc_ref_clk_sel[8:6] = modulous – 1
  • . ssc_ref_clk_sel[5:0] = 2's complement push amount.
3 Reserved Reserved
2-0 PHY_SSC_RANGE Spread Spectrum Clock Range.

Selects the range of spread spectrum modulation when ssc_en is asserted and the PHY is spreading the high-speed transmit clocks. Applies a fixed offset to the phase accumulator.

千亿体育app官网登录(中国)官方网站IOS/安卓通用版/手机APP | 米乐app下载官网（中国）|ios|Android/通用版APP最新版 | 米乐|米乐·M6（中国大陆）官方网站 | 千亿体育登陆地址 | 华体会体育（中国）HTH·官方网站 | 千赢qy国际_全站最新版千赢qy国际V6.2.14安卓/IOS下载 | 18新利网v1.2.5|中国官方网站 | bob电竞真人（中国官网）安卓/ios苹果/电脑版【1.97.95版下载】 | 千亿体育app官方下载(中国)官方网站IOS/安卓/手机APP下载安装 |