ZHCSBT2G November   2012  – October 2017 66AK2H06 , 66AK2H12 , 66AK2H14

PRODUCTION DATA.  

  1. 1 器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
      1. 1.3.1 KeyStone II 的增强功能
    4. 1.4 功能方框图
  2. 2 修订历史记录
  3. 3 Device Comparison
    1. 3.1 Related Products
  4. 4 Terminal Configuration and Functions
    1. 4.1 Package Terminals
    2. 4.2 Pin Map
    3. 4.3 Terminal Functions
    4. 4.4 Pullup/Pulldown Resistors
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Power Consumption Summary
    5. 5.5 Electrical Characteristics
    6. 5.6 Thermal Resistance Characteristics for PBGA Package [AAW]
    7. 5.7 Power Supply to Peripheral I/O Mapping
  6. 6 C66x CorePac
    1. 6.1 C66x DSP CorePac
    2. 6.2 Memory Architecture
      1. 6.2.1 L1P Memory
      2. 6.2.2 L1D Memory
      3. 6.2.3 L2 Memory
      4. 6.2.4 Multicore Shared Memory SRAM
      5. 6.2.5 L3 Memory
    3. 6.3 Memory Protection
    4. 6.4 Bandwidth Management
    5. 6.5 Power-Down Control
    6. 6.6 C66x CorePac Revision
      1. Table 6-2 CorePac Revision ID Register (MM_REVID) Field Descriptions
    7. 6.7 C66x CorePac Register Descriptions
  7. 7 ARM CorePac
    1. 7.1 Features
    2. 7.2 System Integration
    3. 7.3 ARM Cortex-A15 Processor
      1. 7.3.1 Overview
      2. 7.3.2 Features
      3. 7.3.3 ARM Interrupt Controller
      4. 7.3.4 Endianess
    4. 7.4 CFG Connection
    5. 7.5 Main TeraNet Connection
    6. 7.6 Clocking and Reset
      1. 7.6.1 Clocking
      2. 7.6.2 Reset
  8. 8 Memory, Interrupts, and EDMA for 66AK2Hxx
    1. 8.1 Memory Map Summary for 66AK2Hxx
    2. 8.2 Memory Protection Unit (MPU) for 66AK2Hxx
      1. 8.2.1 MPU Registers
        1. 8.2.1.1 MPU Register Map
        2. 8.2.1.2 Device-Specific MPU Registers
          1. 8.2.1.2.1 Configuration Register (CONFIG)
            1. Table 8-9 Configuration Register Field Descriptions
      2. 8.2.2 MPU Programmable Range Registers
        1. 8.2.2.1 Programmable Range n Start Address Register (PROGn_MPSAR)
          1. Table 8-10 Programmable Range n Start Address Register Field Descriptions
        2. 8.2.2.2 Programmable Range n - End Address Register (PROGn_MPEAR)
          1. Table 8-14 Programmable Range n End Address Register Field Descriptions
        3. 8.2.2.3 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPAR)
          1. Table 8-18 Programmable Range n Memory Protection Page Attribute Register Field Descriptions
    3. 8.3 Interrupts for 66AK2Hxx
      1. 8.3.1 Interrupt Sources and Interrupt Controller
      2. 8.3.2 CIC Registers
        1. 8.3.2.1 CIC0 Register Map
        2. 8.3.2.2 CIC1 Register Map
        3. 8.3.2.3 CIC2 Register Map
      3. 8.3.3 Inter-Processor Register Map
      4. 8.3.4 NMI and LRESET
    4. 8.4 Enhanced Direct Memory Access (EDMA3) Controller for 66AK2Hxx
      1. 8.4.1 EDMA3 Device-Specific Information
      2. 8.4.2 EDMA3 Channel Controller Configuration
      3. 8.4.3 EDMA3 Transfer Controller Configuration
      4. 8.4.4 EDMA3 Channel Synchronization Events
  9. 9 System Interconnect
    1. 9.1 Internal Buses and Switch Fabrics
    2. 9.2 Switch Fabric Connections Matrix - Data Space
    3. 9.3 TeraNet Switch Fabric Connections Matrix - Configuration Space
    4. 9.4 Bus Priorities
  10. 10Device Boot and Configuration
    1. 10.1 Device Boot
      1. 10.1.1 Boot Sequence
      2. 10.1.2 Boot Modes Supported
        1. 10.1.2.1 Boot Device Field
          1. Table 10-3 Boot Mode Pins: Boot Device Values
        2. 10.1.2.2 Device Configuration Field
          1. 10.1.2.2.1 Sleep Boot Mode Configuration
            1. Table 10-4 Sleep Boot Configuration Field Descriptions
          2. 10.1.2.2.2 I2C Boot Device Configuration
            1. 10.1.2.2.2.1 I2C Passive Mode
              1. Table 10-5 I2C Passive Mode Device Configuration Field Descriptions
            2. 10.1.2.2.2.2 I2C Master Mode
              1. Table 10-6 I2C Master Mode Device Configuration Field Descriptions
          3. 10.1.2.2.3 SPI Boot Device Configuration
            1. Table 10-7 SPI Device Configuration Field Descriptions
          4. 10.1.2.2.4 EMIF Boot Device Configuration
            1. Table 10-8 EMIF Boot Device Configuration Field Descriptions
          5. 10.1.2.2.5 NAND Boot Device Configuration
            1. Table 10-9 NAND Boot Device Configuration Field Descriptions
        3. 10.1.2.3 Serial Rapid I/O Boot Device Configuration
          1. Table 10-10 Serial Rapid I/O Boot Device Configuration Field Descriptions
        4. 10.1.2.4 Ethernet (SGMII) Boot Device Configuration
          1. Table 10-11 Ethernet (SGMII) Boot Device Configuration Field Descriptions
          2. 10.1.2.4.1   PCIe Boot Device Configuration
            1. Table 10-12 PCIe Boot Device Configuration Field Descriptions
          3. 10.1.2.4.2   HyperLink Boot Device Configuration
            1. Table 10-14 HyperLink Boot Device Configuration Field Descriptions
          4. 10.1.2.4.3   UART Boot Device Configuration
            1. Table 10-15 UART Boot Configuration Field Descriptions
        5. 10.1.2.5 Boot Parameter Table
          1. 10.1.2.5.1  EMIF16 Boot Parameter Table
          2. 10.1.2.5.2  SRIO Boot Parameter Table
          3. 10.1.2.5.3  Ethernet Boot Parameter Table
          4. 10.1.2.5.4  PCIe Boot Parameter Table
          5. 10.1.2.5.5  I2C Boot Parameter Table
          6. 10.1.2.5.6  SPI Boot Parameter Table
          7. 10.1.2.5.7  HyperLink Boot Parameter Table
          8. 10.1.2.5.8  UART Boot Parameter Table
          9. 10.1.2.5.9  NAND Boot Parameter Table
          10. 10.1.2.5.10 DDR3 Configuration Table
        6. 10.1.2.6 Second-Level Bootloaders
      3. 10.1.3 SoC Security
      4. 10.1.4 System PLL Settings
        1. 10.1.4.1 ARM CorePac System PLL Settings
    2. 10.2 Device Configuration
      1. 10.2.1 Device Configuration at Device Reset
      2. 10.2.2 Peripheral Selection After Device Reset
      3. 10.2.3 Device State Control Registers
        1. 10.2.3.1  Device Status (DEVSTAT) Register
          1. Table 10-31 Device Status Register Field Descriptions
        2. 10.2.3.2  Device Configuration Register
          1. Table 10-32 Device Configuration Register Field Descriptions
        3. 10.2.3.3  JTAG ID (JTAGID) Register Description
          1. Table 10-33 JTAG ID Register Field Descriptions
        4. 10.2.3.4  Kicker Mechanism (KICK0 and KICK1) Register
        5. 10.2.3.5  DSP Boot Address Register (DSP_BOOT_ADDRn)
          1. Table 10-1 DSP BOOT Address Register (DSP_BOOT_ADDRn)
        6. 10.2.3.6  LRESETNMI PIN Status (LRSTNMIPINSTAT) Register
          1. Table 10-35 LRESETNMI PIN Status Register Field Descriptions
        7. 10.2.3.7  LRESETNMI PIN Status Clear (LRSTNMIPINSTAT_CLR) Register
          1. Table 10-36 LRESETNMI PIN Status Clear Register Field Descriptions
        8. 10.2.3.8  Reset Status (RESET_STAT) Register
          1. Table 10-37 Reset Status Register Field Descriptions
        9. 10.2.3.9  Reset Status Clear (RESET_STAT_CLR) Register
          1. Table 10-38 Reset Status Clear Register Field Descriptions
        10. 10.2.3.10 Boot Complete (BOOTCOMPLETE) Register
          1. Table 10-39 Boot Complete Register Field Descriptions
        11. 10.2.3.11 Power State Control (PWRSTATECTL) Register
          1. Table 10-40 Power State Control Register Field Descriptions
        12. 10.2.3.12 NMI Event Generation to C66x CorePac (NMIGRx) Register
          1. Table 10-41 NMI Generation Register Field Descriptions
        13. 10.2.3.13 IPC Generation (IPCGRx) Registers
          1. Table 10-42 IPC Generation Registers Field Descriptions
        14. 10.2.3.14 IPC Acknowledgment (IPCARx) Registers
          1. Table 10-43 IPC Acknowledgment Registers Field Descriptions
        15. 10.2.3.15 IPC Generation Host (IPCGRH) Register
          1. Table 10-44 IPC Generation Registers Field Descriptions
        16. 10.2.3.16 IPC Acknowledgment Host (IPCARH) Register
          1. Table 10-45 IPC Acknowledgment Register Field Descriptions
        17. 10.2.3.17 Timer Input Selection Register (TINPSEL)
          1. Table 10-46 Timer Input Selection Field Description
        18. 10.2.3.18 Timer Output Selection Register (TOUTPSEL)
          1. Table 10-47 Timer Output Selection Register Field Descriptions
        19. 10.2.3.19 Reset Mux (RSTMUXx) Register
          1. Table 10-48 Reset Mux Register Field Descriptions
        20. 10.2.3.20 Device Speed (DEVSPEED) Register
          1. Table 10-49 Device Speed Register Field Descriptions
        21. 10.2.3.21 ARM Endian Configuration Register 0 (ARMENDIAN_CFGr_0), r=0..7
          1. Table 10-50 ARM Endian Configuration Register 0 Field Descriptions
        22. 10.2.3.22 ARM Endian Configuration Register 1 (ARMENDIAN_CFGr_1), r=0..7
          1. Table 10-51 ARM Endian Configuration Register 1 Field Descriptions
        23. 10.2.3.23 ARM Endian Configuration Register 2 (ARMENDIAN_CFGr_2), r=0..7
          1. Table 10-52 ARM Endian Configuration Register 2 Field Descriptions
        24. 10.2.3.24 Chip Miscellaneous Control (CHIP_MISC_CTL0) Register
          1. Table 10-53 Chip Miscellaneous Control Register Field Descriptions
        25. 10.2.3.25 Chip Miscellaneous Control (CHIP_MISC_CTL1) Register
          1. Table 10-54 Chip Miscellaneous Control Register Field Descriptions
        26. 10.2.3.26 System Endian Status Register (SYSENDSTAT)
          1. Table 10-55 System Endian Status Register Field Descriptions
        27. 10.2.3.27 SYNECLK_PINCTL Register
          1. Table 10-56 SYNECLK_PINCTL Register Field Descriptions
        28. 10.2.3.28 USB PHY Control (USB_PHY_CTLx) Registers
          1. Table 10-57 USB_PHY_CTL0 Register Field Descriptions
          2. Table 10-58 USB_PHY_CTL1 Register Field Descriptions
          3. Table 10-59 USB_PHY_CTL2 Register Field Descriptions
          4. Table 10-60 USB_PHY_CTL3 Register Field Descriptions
          5. Table 10-61 USB_PHY_CTL4 Register Field Descriptions
          6. Table 10-62 USB_PHY_CTL5 Register Field Descriptions
  11. 1166AK2Hxx Peripheral Information
    1. 11.1  Recommended Clock and Control Signal Transition Behavior
    2. 11.2  Power Supplies
      1. 11.2.1 Power-Up Sequencing
        1. 11.2.1.1 Core-Before-IO Power Sequencing
        2. 11.2.1.2 IO-Before-Core Power Sequencing
        3. 11.2.1.3 Prolonged Resets
        4. 11.2.1.4 Clocking During Power Sequencing
      2. 11.2.2 Power-Down Sequence
      3. 11.2.3 Power Supply Decoupling and Bulk Capacitor
      4. 11.2.4 SmartReflex
        1. Table 11-5 SmartReflex 4-Pin 6-bit VID Interface Switching Characteristics
    3. 11.3  Power Sleep Controller (PSC)
      1. 11.3.1 Power Domains
      2. 11.3.2 Clock Domains
      3. 11.3.3 PSC Register Memory Map
    4. 11.4  Reset Controller
      1. 11.4.1 Power-on Reset
      2. 11.4.2 Hard Reset
      3. 11.4.3 Soft Reset
      4. 11.4.4 Local Reset
      5. 11.4.5 ARM CorePac Reset
      6. 11.4.6 Reset Priority
      7. 11.4.7 Reset Controller Register
      8. 11.4.8 Reset Electrical Data and Timing
        1. Table 11-10 Reset Timing Requirements
        2. Table 11-11 Reset Switching Characteristics
        3. Table 11-12 Boot Configuration Timing Requirements
    5. 11.5  Main PLL, ARM PLL, DDR3A PLL, DDR3B PLL, PASS PLL and the PLL Controllers
      1. 11.5.1 Main PLL Controller Device-Specific Information
        1. 11.5.1.1 Internal Clocks and Maximum Operating Frequencies
        2. 11.5.1.2 Local Clock Dividers
        3. 11.5.1.3 Module Clock Input
        4. 11.5.1.4 Main PLL Controller Operating Modes
        5. 11.5.1.5 Main PLL Stabilization, Lock, and Reset Times
      2. 11.5.2 PLL Controller Memory Map
        1. 11.5.2.1 PLL Secondary Control Register (SECCTL)
          1. Table 11-16 PLL Secondary Control Register Field Descriptions
        2. 11.5.2.2 PLL Controller Divider Register (PLLDIV3 and PLLDIV4)
          1. Table 11-17 PLL Controller Divider Register Field Descriptions
        3. 11.5.2.3 PLL Controller Clock Align Control Register (ALNCTL)
          1. Table 11-18 PLL Controller Clock Align Control Register Field Descriptions
        4. 11.5.2.4 PLLDIV Divider Ratio Change Status Register (DCHANGE)
          1. Table 11-19 PLLDIV Divider Ratio Change Status Register Field Descriptions
        5. 11.5.2.5 SYSCLK Status Register (SYSTAT)
          1. Table 11-20 SYSCLK Status Register Field Descriptions
        6. 11.5.2.6 Reset Type Status Register (RSTYPE)
          1. Table 11-21 Reset Type Status Register Field Descriptions
        7. 11.5.2.7 Reset Control Register (RSTCTRL)
          1. Table 11-22 Reset Control Register Field Descriptions
        8. 11.5.2.8 Reset Configuration Register (RSTCFG)
          1. Table 11-23 Reset Configuration Register Field Descriptions
        9. 11.5.2.9 Reset Isolation Register (RSISO)
          1. Table 11-24 Reset Isolation Register Field Descriptions
      3. 11.5.3 Main PLL Control Registers
        1. Table 11-25 Main PLL Control Register 0 (MAINPLLCTL0) Field Descriptions
        2. Table 11-26 Main PLL Control Register 1 (MAINPLLCTL1) Field Descriptions
      4. 11.5.4 ARM PLL Control Registers
        1. Table 11-27 ARM PLL Control Register 0 Field Descriptions
        2. Table 11-28 ARM PLL Control Register 1 Field Descriptions
      5. 11.5.5 Main PLL Controller, ARM, SRIO, HyperLink, PCIe, USB Clock Input Electrical Data and Timing
        1. Table 11-29 Main PLL Controller, ARM, SRIO, HyperLink, PCIe, USB Clock Input Timing Requirements
    6. 11.6  DDR3A PLL and DDR3B PLL
      1. 11.6.1 DDR3A PLL and DDR3B PLL Control Registers
        1. Table 11-30 DDR3A PLL and DDR3B PLL Control Register 0 Field Descriptions
        2. Table 11-31 DDR3A PLL and DDR3B PLL Control Register 1 Field Descriptions
      2. 11.6.2 DDR3A PLL and DDR3B PLL Device-Specific Information
      3. 11.6.3 DDR3 PLL Input Clock Electrical Data and Timing
        1. Table 11-32 DDR3 PLL DDRCLK(N|P) Timing Requirements
    7. 11.7  PASS PLL
      1. 11.7.1 PASS PLL Local Clock Dividers
      2. 11.7.2 PASS PLL Control Registers
        1. Table 11-33 PASS PLL Control Register 0 Field Descriptions (PASSPLLCTL0)
        2. Table 11-34 PASS PLL Control Register 1 Field Descriptions (PASSPLLCTL1)
      3. 11.7.3 PASS PLL Device-Specific Information
      4. 11.7.4 PASS PLL Input Clock Electrical Data and Timing
        1. Table 11-35 PASS PLL Timing Requirements
    8. 11.8  External Interrupts
      1. 11.8.1 External Interrupts Electrical Data and Timing
        1. Table 11-36 NMI and LRESET Timing Requirements
    9. 11.9  DDR3A and DDR3B Memory Controllers
      1. 11.9.1 DDR3 Memory Controller Device-Specific Information
      2. 11.9.2 DDR3 Slew Rate Control
      3. 11.9.3 DDR3 Memory Controller Electrical Data and Timing
    10. 11.10 I2C Peripheral
      1. 11.10.1 I2C Device-Specific Information
      2. 11.10.2 I2C Peripheral Register Description
      3. 11.10.3 I2C Electrical Data and Timing
        1. Table 11-38 I2C Timing Requirements
        2. Table 11-39 I2C Switching Characteristics
    11. 11.11 SPI Peripheral
      1. 11.11.1 SPI Electrical Data and Timing
        1. Table 11-40 SPI Timing Requirements
        2. Table 11-41 SPI Switching Characteristics
    12. 11.12 HyperLink Peripheral
      1. Table 11-42 HyperLink Peripheral Timing Requirements
      2. Table 11-43 HyperLink Peripheral Switching Characteristics
    13. 11.13 UART Peripheral
      1. Table 11-44 UART Timing Requirements
      2. Table 11-45 UART Switching Characteristics
    14. 11.14 PCIe Peripheral
    15. 11.15 Packet Accelerator
    16. 11.16 Security Accelerator
    17. 11.17 Network Coprocessor Gigabit Ethernet (GbE) Switch Subsystem
      1. Table 11-46 MACID1 Register Field Descriptions
      2. Table 11-47 MACID2 Register Field Descriptions
      3. Table 11-48 RFTCLK Select Register Field Descriptions
    18. 11.18 SGMII and XFI Management Data Input/Output (MDIO)
      1. Table 11-49 MDIO Timing Requirements
      2. Table 11-50 MDIO Switching Characteristics
    19. 11.19 Ten-Gigabit Ethernet (10GbE) Switch Subsystem
      1. 11.19.1 10GbE Supported Features
    20. 11.20 Timers
      1. 11.20.1 Timers Device-Specific Information
      2. 11.20.2 Timers Electrical Data and Timing
        1. Table 11-51 Timer Input Timing Requirements
        2. Table 11-52 Timer Output Switching Characteristics
    21. 11.21 Serial RapidIO (SRIO) Port
      1. 11.21.1 Serial RapidIO Device-Specific Information
    22. 11.22 General-Purpose Input/Output (GPIO)
      1. 11.22.1 GPIO Device-Specific Information
      2. 11.22.2 GPIO Peripheral Register Description
      3. 11.22.3 GPIO Electrical Data and Timing
        1. Table 11-54 GPIO Input Timing Requirements
        2. Table 11-55 GPIO Output Switching Characteristics
    23. 11.23 Semaphore2
    24. 11.24 Universal Serial Bus 3.0 (USB 3.0)
    25. 11.25 EMIF16 Peripheral
      1. 11.25.1 EMIF16 Electrical Data and Timing
        1. Table 11-56 EMIF16 Asynchronous Memory Timing Requirements
    26. 11.26 Emulation Features and Capability
      1. 11.26.1 Chip-Level Features
        1. 11.26.1.1 ARM Subsystem Features
        2. 11.26.1.2 DSP Features
      2. 11.26.2 ICEPick Module
        1. 11.26.2.1 ICEPick Dynamic Tap Insertion
    27. 11.27 Debug Port (EMUx)
      1. 11.27.1 Concurrent Use of Debug Port
      2. 11.27.2 Master ID for Hardware and Software Messages
      3. 11.27.3 SoC Cross-Triggering Connection
      4. 11.27.4 Peripherals-Related Debug Requirement
      5. 11.27.5 Advanced Event Triggering (AET)
      6. 11.27.6 Trace
        1. 11.27.6.1 Trace Electrical Data and Timing
          1. Table 11-66 Trace Switching Characteristics
      7. 11.27.7 IEEE 1149.1 JTAG
        1. 11.27.7.1 IEEE 1149.1 JTAG Compatibility Statement
        2. 11.27.7.2 JTAG Electrical Data and Timing
          1. Table 11-67 JTAG Test Port Timing Requirements
          2. Table 11-68 JTAG Test Port Switching Characteristics
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Tools and Software
    3. 12.3 Documentation Support
    4. 12.4 Related Links
    5. 12.5 Community Resources
    6. 12.6 商标
    7. 12.7 静电放电警告
    8. 12.8 术语表
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Packaging Information

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机械数据 (封装 | 引脚)
  • AAW|1517
散热焊盘机械数据 (封装 | 引脚)
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8.3.1 Interrupt Sources and Interrupt Controller

The CPU interrupts on the 66AK2Hxx device are configured through the C66x CorePac Interrupt Controller. The Interrupt Controller allows for up to 128 system events to be programmed to any of the 12 CPU interrupt inputs (CPUINT4 - CPUINT15), the CPU exception input (EXCEP), or the advanced emulation logic. The 128 system events consist of both internally-generated events (within the CorePac) and chip-level events.

Additional system events are routed to each of the C66x CorePacs to provide chip-level events that are not required as CPU interrupts/exceptions to be routed to the Interrupt Controller as emulation events. In addition, error-class events or infrequently used events are also routed through the system event router to offload the C66x CorePac interrupt selector. This is accomplished through the CorePac Interrupt Controller blocks, CIC[2:0]. This is clocked using CPU/6.

The event controllers consist of simple combination logic to provide additional events to each C66x CorePac, ARM GIC (ARM Generic Interrupt Controller) plus the EDMA3CC. CIC0 has 104 event outputs which provides 20 broadcast events and 18 additional events to each of the C66x CorePacs, 0 through 3. Similarly, CIC1 has 104 event outputs which provides 20 broadcast events and 18 additional events to each of the C66x CorePacs, 4 through 7 (66AK2H12/14 only). CIC2 has 103 event outputs which provides 8, 20, 8, 8, 8, and 16 events to EDMA3CC0, EDMA3CC1, EDMA3C2, EDMA3CC3, EDMA3CC4, and HyperLinks respectively.

The events that are routed to the C66x CorePacs for Advanced Event Triggering (AET) purposes from those EDMA3CC and FSYNC events that are not otherwise provided to each C66x CorePac.

Modules such as CP_MPU, BOOT_CFG, and CP_Tracer have level interrupts and EOI handshaking interface. The EOI value is 0 for CP_MPU, BOOT_CFG, and CP_Tracer.

Figure 8-4 and Figure 8-5 show the 66AK2Hxx interrupt topologies.

66AK2H14 66AK2H12 66AK2H06 Interrupt_Topology_B_D_66AK2H12-14.gifFigure 8-4 66AK2H14/12 Interrupt Topology
66AK2H14 66AK2H12 66AK2H06 Interrupt_Topology_B_D_66AK2H06.gifFigure 8-5 66AK2H06 Interrupt Topology

Table 8-22 shows the mapping of primary events to C66x Corepac.

Table 8-22 System Event Mapping — C66x CorePac Primary Interrupts

EVENT NO. EVENT NAME DESCRIPTION
0 EVT0 Event combiner 0 output
1 EVT1 Event combiner 1 output
2 EVT2 Event combiner 2 output
3 EVT3 Event combiner 3 output
4 TETB_HFULLINTN TETB is half full
5 TETB_FULLINTN TETB is full
6 TETB_ACQINTN TETB Acquisition complete interrupt
7 TETB_OVFLINTN TETB Overflow condition interrupt
8 TETB_UNFLINTN TETB Underflow condition interrupt
9 EMU_DTDMA Emulation interrupt for host scan, DTDMA transfer complete and AET
10 MSMC_MPF_ERRORN Memory protection fault indicators for system master PrivID = 0 (C66x CorePac)
11 Reserved Reserved
12 Reserved Reserved
13 IDMA0 IDMA channel 0 interrupt
14 IDMA1 IDMA channel 1 interrupt
15 SEM_ERRN Semaphore error interrupt
16 SEM_INTN Semaphore interrupt
17 PCIE_INT4_PLUS_N PCIE0 MSI interrupt
18 Reserved Reserved
19 Reserved Reserved
20 SRIO_INTDST16_PLUS_N SRIO interrupt
21 Reserved Reserved
22 Reserved Reserved
23 CIC_OUT35 CIC Interrupt Controller output(1)
24 CIC_2_OUT102 CIC Interrupt Controller output
25 CIC_2_OUT94_PLUS_N(2) CIC Interrupt Controller output
26 CIC_OUT68_PLUS_10_MUL_N(2) CIC Interrupt Controller output(1)
27 CIC_OUT69_PLUS_10_MUL_N(2) CIC Interrupt Controller output(1)
28 CIC_OUT70_PLUS_10_MUL_N(2) CIC Interrupt Controller output(1)
29 CIC_OUT71_PLUS_10_MUL_N(2) CIC Interrupt Controller output(1)
30 CIC_OUT72_PLUS_10_MUL_N(2) CIC Interrupt Controller output(1)
31 CIC_OUT73_PLUS_10_MUL_N(2) CIC Interrupt Controller output(1)
32 CIC_OUT16 CIC Interrupt Controller output(1)
33 CIC_OUT17 CIC Interrupt Controller output(1)
34 CIC_OUT18 CIC Interrupt Controller output(1)
35 CIC_OUT19 CIC Interrupt Controller output(1)
36 CIC_OUT20 CIC Interrupt Controller output(1)
37 CIC_OUT21 CIC Interrupt Controller output(1)
38 CIC_OUT22 CIC Interrupt Controller output(1)
39 CIC_OUT23 CIC Interrupt Controller output(1)
40 CIC_OUT32 CIC Interrupt Controller output(1)
41 CIC_OUT33 CIC Interrupt Controller output(1)
42 CIC_OUT13_PLUS_16_MUL_N(2) CIC Interrupt Controller output(1)
43 CIC_OUT14_PLUS_16_MUL_N(2) CIC Interrupt Controller output(1)
44 CIC_OUT15_PLUS_16_MUL_N(2) CIC Interrupt Controller output(1)
45 CIC_OUT64_PLUS_10_MUL_N(2) CIC Interrupt Controller output(1)
46 CIC_OUT65_PLUS_10_MUL_N(2) CIC Interrupt Controller output(1)
47 CIC_OUT66_PLUS_10_MUL_N(2) CIC Interrupt Controller output(1)
48 QMSS_INTD_1_HIGH_N(2) Navigator 1 accumulated hi-priority interrupt 0
49 QMSS_INTD_1_HIGH_8_PLUS_N(2) Navigator 1 accumulated hi-priority interrupt 8
50 QMSS_INTD_1_HIGH_16_PLUS_N(2) Navigator 1 accumulated hi-priority interrupt 16
51 QMSS_INTD_1_HIGH_24_PLUS_N(2) Navigator 1 accumulated hi-priority interrupt 24
52 QMSS_INTD_2_HIGH_N(2) Navigator 2 accumulated hi-priority interrupt 0
53 QMSS_INTD_2_HIGH_8_PLUS_N(2) Navigator 2 accumulated hi-priority interrupt 8
54 QMSS_INTD_2_HIGH_16_PLUS_N(2) Navigator 2 accumulated hi-priority interrupt 16
55 QMSS_INTD_2_HIGH_24_PLUS_N(2) Navigator 2 accumulated hi-priority interrupt 24
56 CIC_OUT0 CIC Interrupt Controller output(1)
57 CIC_OUT1 CIC Interrupt Controller output(1)
58 CIC_OUT2 CIC Interrupt Controller output(1)
59 CIC_OUT3 CIC Interrupt Controller output(1)
60 CIC_OUT4 CIC Interrupt Controller output(1)
61 CIC_OUT5 CIC Interrupt Controller output(1)
62 CIC_OUT6 CIC Interrupt Controller output(1)
63 CIC_OUT7 CIC Interrupt Controller output(1)
64 TIMER_N_INTL Local timer interrupt low
65 TIMER_N_INTH Local timer interrupt high
66 TIMER_8_INTL Timer interrupt low
67 TIMER_8_INTH Timer interrupt high
68 TIMER_9_INTL Timer interrupt low
69 TIMER_9_INTH Timer interrupt high
70 TIMER_10_INTL Timer interrupt low
71 TIMER_10_INTH Timer interrupt high
72 TIMER_11_INTL Timer interrupt low
73 TIMER_11_INTH Timer interrupt high
74 CIC_OUT8_PLUS_16_MUL_N(2) CIC Interrupt Controller output(1)
75 CIC_OUT9_PLUS_16_MUL_N(2) CIC Interrupt Controller output(1)
76 CIC_OUT10_PLUS_16_MUL_N(2) CIC Interrupt Controller output(1)
77 CIC_OUT11_PLUS_16_MUL_N(2) CIC Interrupt Controller output(1)
78 TIMER_14_INTL Timer interrupt low
79 TIMER_14_INTH Timer interrupt high
80 TIMER_15_INTL Timer interrupt low
81 TIMER_15_INTH Timer interrupt high
82 GPIO_INT8 Local GPIO interrupt
83 GPIO_INT9 Local GPIO interrupt
84 GPIO_INT10 Local GPIO interrupt
85 GPIO_INT11 Local GPIO interrupt
86 GPIO_INT12 Local GPIO interrupt
87 Reserved Reserved
88 Reserved Reserved
89 Reserved Reserved
90 Reserved Reserved
91 Reserved Reserved
92 Reserved Reserved
93 Reserved Reserved
94 Reserved Reserved
95 CIC_OUT67_PLUS_10_MUL_N(2) CIC Interrupt Controller output(1)
96 INTERR Dropped C66x CorePac interrupt event
97 EMC_IDMAERR Invalid IDMA parameters
98 Reserved Reserved
99 CIC_2_SPECIAL_BROADCAST CIC Interrupt Controller output
100 EFIINT0 EFI interrupt from Side A
101 EFIINT1 EFI interrupt from Side B
102 GPIO_INT13 Local GPIO interrupt
103 GPIO_INT14 Local GPIO interrupt
104 GPIO_INT15 Local GPIO interrupt
105 IPC_GRN Boot CFG
106 GPIO_INTN GPIO interrupt
107 CIC_OUT12_PLUS_16_MUL_N(2) CIC Interrupt Controller output(1)
108 CIC_OUT34 CIC Interrupt Controller output(1)
109 CIC_2_OUT13 CIC Interrupt Controller output
110 MDMAERREVT DMA internal bus error event
111 Reserved Reserved
112 EDMACC_0_4_TC_AET_INT EDMA3CC0_4 AET event
113 PMC_ED Single bit error detected during DMA read
114 EDMACC_1_2_TC_AET_INT EDMA3CC1_2 AET event
115 EDMACC_1_3_TC_AET_INT EDMA3CC3_4 AET event
116 UMC_ED1 Corrected bit error detected
117 UMC_ED2 Uncorrected bit error detected
118 PDC_INT Power down sleep interrupt
119 SYS_CMPA SYS CPU MP fault event
120 PMC_CMPA CPU memory protection fault
121 PMC_DMPA DMA memory protection fault
122 DMC_CMPA CPU memory protection fault
123 DMC_DMPA DMA memory protection fault
124 UMC_CMPA CPU memory protection fault
125 UMC_DMPA DMA memory protection fault
126 EMC_CMPA CPU memory protection fault
127 EMC_BUSERR Bus error interrupt
(1) For C66x CorePac[0-3], this generic primary interrupt comes from CIC0 and for C66x CorePac[4-7], this generic primary interrupt comes from CIC1.
(2) N = core number.

NOTE

Event No. 0 is identical to ARM GIC interrupt ID 0.

Table 8-23 System Event Mapping — ARM CorePac Interrupts

EVENT NO. EVENT NAME DESCRIPTION
0 RSTMUX_INT8 Boot config watchdog timer expiration (timer 16) event for ARM Core 0
1 RSTMUX_INT9 Boot config watchdog timer expiration (timer 17) event for ARM Core 1
2 RSTMUX_INT10 Boot config watchdog timer expiration (timer 18) event for ARM Core 2(1)
3 RSTMUX_INT11 Boot config watchdog timer expiration (timer 19) event for ARM Core 3(1)
4 IPC_GR8 Boot config IPCG
5 IPC_GR9 Boot config IPCG
6 IPC_GR10 Boot config IPCG
7 IPC_GR11 Boot config IPCG
8 SEM_INT8 Semaphore interrupt
9 SEM_INT9 Semaphore interrupt
10 SEM_INT10 Semaphore interrupt
11 SEM_INT11 Semaphore interrupt
12 SEM_ERR8 Semaphore error interrupt
13 SEM_ERR9 Semaphore error interrupt
14 SEM_ERR10 Semaphore error interrupt
15 SEM_ERR11 Semaphore error interrupt
16 MSMC_MPF_ERROR8 Memory protection fault indicators for system master PrivID = 8
17 MSMC_MPF_ERROR9 Memory protection fault indicators for system master PrivID = 9
18 MSMC_MPF_ERROR10 Memory protection fault indicators for system master PrivID = 10
19 MSMC_MPF_ERROR11 Memory protection fault indicators for system master PrivID = 11
20 ARM_NPMUIRQ0 ARM performance monitoring unit interrupt request
21 ARM_NPMUIRQ1 ARM performance monitoring unit interrupt request
22 ARM_NPMUIRQ2 ARM performance monitoring unit interrupt request
23 ARM_NPMUIRQ3 ARM performance monitoring unit interrupt request
24 ARM_NINTERRIRQ ARM internal memory ECC error interrupt request
25 ARM_NAXIERRIRQ ARM bus error interrupt request
26 PCIE_INT0 PCIE legacy INTA interrupt
27 PCIE_INT1 PCIE legacy INTB interrupt
28 PCIE_INT2 PCIE legacy INTC interrupt
29 PCIE_INT3 PCIE legacy INTD interrupt
30 PCIE_INT4 PCIE MSI interrupt
31 PCIE_INT5 PCIE MSI interrupt
32 PCIE_INT6 PCIE MSI interrupt
33 PCIE_INT7 PCIE MSI interrupt
34 PCIE_INT8 PCIE MSI interrupt
35 PCIE_INT9 PCIE MSI interrupt
36 PCIE_INT10 PCIE MSI interrupt
37 PCIE_INT11 PCIE MSI interrupt
38 PCIE_INT12 PCIE error interrupt
39 PCIE_INT13 PCIE power management interrupt
40 QMSS_QUE_PEND_658 Navigator transmit queue pending event for indicated queue
41 QMSS_QUE_PEND_659 Navigator transmit queue pending event for indicated queue
42 QMSS_QUE_PEND_660 Navigator transmit queue pending event for indicated queue
43 QMSS_QUE_PEND_661 Navigator transmit queue pending event for indicated queue
44 QMSS_QUE_PEND_662 Navigator transmit queue pending event for indicated queue
45 QMSS_QUE_PEND_663 Navigator transmit queue pending event for indicated queue
46 QMSS_QUE_PEND_664 Navigator transmit queue pending event for indicated queue
47 QMSS_QUE_PEND_665 Navigator transmit queue pending event for indicated queue
48 QMSS_QUE_PEND_8704 Navigator transmit queue pending event for indicated queue
49 QMSS_QUE_PEND_8705 Navigator transmit queue pending event for indicated queue
50 QMSS_QUE_PEND_8706 Navigator transmit queue pending event for indicated queue
51 QMSS_QUE_PEND_8707 Navigator transmit queue pending event for indicated queue
52 QMSS_QUE_PEND_8708 Navigator transmit queue pending event for indicated queue
53 QMSS_QUE_PEND_8709 Navigator transmit queue pending event for indicated queue
54 QMSS_QUE_PEND_8710 Navigator transmit queue pending event for indicated queue
55 QMSS_QUE_PEND_8711 Navigator transmit queue pending event for indicated queue
56 QMSS_QUE_PEND_8712 Navigator transmit queue pending event for indicated queue
57 QMSS_QUE_PEND_8713 Navigator transmit queue pending event for indicated queue
58 QMSS_QUE_PEND_8714 Navigator transmit queue pending event for indicated queue
59 QMSS_QUE_PEND_8715 Navigator transmit queue pending event for indicated queue
60 QMSS_QUE_PEND_8716 Navigator transmit queue pending event for indicated queue
61 QMSS_QUE_PEND_8717 Navigator transmit queue pending event for indicated queue
62 QMSS_QUE_PEND_8718 Navigator transmit queue pending event for indicated queue
63 QMSS_QUE_PEND_8719 Navigator transmit queue pending event for indicated queue
64 QMSS_QUE_PEND_8720 Navigator transmit queue pending event for indicated queue
65 QMSS_QUE_PEND_8721 Navigator transmit queue pending event for indicated queue
66 QMSS_QUE_PEND_8722 Navigator transmit queue pending event for indicated queue
67 QMSS_QUE_PEND_8723 Navigator transmit queue pending event for indicated queue
68 QMSS_QUE_PEND_8724 Navigator transmit queue pending event for indicated queue
69 QMSS_QUE_PEND_8725 Navigator transmit queue pending event for indicated queue
70 QMSS_QUE_PEND_8726 Navigator transmit queue pending event for indicated queue
71 QMSS_QUE_PEND_8727 Navigator transmit queue pending event for indicated queue
72 QMSS_QUE_PEND_8728 Navigator transmit queue pending event for indicated queue
73 QMSS_QUE_PEND_8729 Navigator transmit queue pending event for indicated queue
74 QMSS_QUE_PEND_8730 Navigator transmit queue pending event for indicated queue
75 QMSS_QUE_PEND_8731 Navigator transmit queue pending event for indicated queue
76 QMSS_QUE_PEND_8732 Navigator transmit queue pending event for indicated queue
77 QMSS_QUE_PEND_8733 Navigator transmit queue pending event for indicated queue
78 QMSS_QUE_PEND_8734 Navigator transmit queue pending event for indicated queue
79 QMSS_QUE_PEND_8735 Navigator transmit queue pending event for indicated queue
80 TIMER_0_INTL Timer interrupt low
81 TIMER_0_INTH Timer interrupt high
82 TIMER_1_INTL Timer interrupt low
83 TIMER_1_INTH Timer interrupt high
84 TIMER_2_INTL Timer interrupt low
85 TIMER_2_INTH Timer interrupt high
86 TIMER_3_INTL Timer interrupt low
87 TIMER_3_INTH Timer interrupt high
88 TIMER_4_INTL Timer interrupt low(1)
89 TIMER_4_INTH Timer interrupt high(1)
90 TIMER_5_INTL Timer interrupt low(1)
91 TIMER_5_INTH Timer interrupt high(1)
92 TIMER_6_INTL Timer interrupt low(1)
93 TIMER_6_INTH Timer interrupt high(1)
94 TIMER_7_INTL Timer interrupt low(1)
95 TIMER_7_INTH Timer interrupt high(1)
96 TIMER_8_INTL Timer interrupt low
97 TIMER_8_INTH Timer interrupt high
98 TIMER_9_INTL Timer interrupt low
99 TIMER_9_INTH Timer interrupt high
100 TIMER_10_INTL Timer interrupt low
101 TIMER_10_INTH Timer interrupt high
102 TIMER_11_INTL Timer interrupt low
103 TIMER_11_INTH Timer interrupt high
104 TIMER_12_INTL Timer interrupt low
105 TIMER_12_INTH Timer interrupt high
106 TIMER_13_INTL Timer interrupt low
107 TIMER_13_INTH Timer interrupt high
108 TIMER_14_INTL Timer interrupt low
109 TIMER_14_INTH Timer interrupt high
110 TIMER_15_INTL Timer interrupt low
111 TIMER_15_INTH Timer interrupt high
112 TIMER_16_INTL Timer interrupt low
113 TIMER_16_INTH Timer interrupt high
114 TIMER_17_INTL Timer interrupt low
115 TIMER_17_INTH Timer interrupt high
116 TIMER_18_INTL Timer interrupt low(1)
117 TIMER_18_INTH Timer interrupt high(1)
118 TIMER_19_INTL Timer interrupt low(1)
119 TIMER_19_INTH Timer interrupt high(1)
120 GPIO_INT0 GPIO interrupt
121 GPIO_INT1 GPIO interrupt
122 GPIO_INT2 GPIO interrupt
123 GPIO_INT3 GPIO interrupt
124 GPIO_INT4 GPIO interrupt
125 GPIO_INT5 GPIO interrupt
126 GPIO_INT6 GPIO interrupt
127 GPIO_INT7 GPIO interrupt
128 GPIO_INT8 GPIO interrupt
129 GPIO_INT9 GPIO interrupt
130 GPIO_INT10 GPIO interrupt
131 GPIO_INT11 GPIO interrupt
132 GPIO_INT12 GPIO interrupt
133 GPIO_INT13 GPIO interrupt
134 GPIO_INT14 GPIO interrupt
135 GPIO_INT15 GPIO interrupt
136 GPIO_INT16 GPIO interrupt
137 GPIO_INT17 GPIO interrupt
138 GPIO_INT18 GPIO interrupt
139 GPIO_INT19 GPIO interrupt
140 GPIO_INT20 GPIO interrupt
141 GPIO_INT21 GPIO interrupt
142 GPIO_INT22 GPIO interrupt
143 GPIO_INT23 GPIO interrupt
144 GPIO_INT24 GPIO interrupt
145 GPIO_INT25 GPIO interrupt
146 GPIO_INT26 GPIO interrupt
147 GPIO_INT27 GPIO interrupt
148 GPIO_INT28 GPIO interrupt
149 GPIO_INT29 GPIO interrupt
150 GPIO_INT30 GPIO interrupt
151 GPIO_INT31 GPIO interrupt
152 SRIO_INT00 SRIO interrupt
153 SRIO_INT01 SRIO interrupt
154 SRIO_INT02 SRIO interrupt
155 SRIO_INT03 SRIO interrupt
156 SRIO_INT04 SRIO interrupt
157 SRIO_INT05 SRIO interrupt
158 SRIO_INT06 SRIO interrupt
159 SRIO_INT07 SRIO interrupt
160 SRIO_INT08 SRIO interrupt
161 SRIO_INT09 SRIO interrupt
162 SRIO_INT10 SRIO interrupt
163 SRIO_INT11 SRIO interrupt
164 SRIO_INT12 SRIO interrupt
165 SRIO_INT13 SRIO interrupt
166 SRIO_INT14 SRIO interrupt
167 SRIO_INT15 SRIO interrupt
168 SRIO_INT16 SRIO interrupt
169 SRIO_INT17 SRIO interrupt
170 SRIO_INT18 SRIO interrupt
171 SRIO_INT19 SRIO interrupt
172 SRIO_INT20 SRIO interrupt
173 SRIO_INT21 SRIO interrupt
174 SRIO_INT22 SRIO interrupt
175 SRIO_INT23 SRIO interrupt
176 SRIO_INT_PKTDMA_0 SRIO interrupt for Packet DMA starvation
177 QMSS_INTD_1_PKTDMA_0 Navigator interrupt for Packet DMA starvation
178 QMSS_INTD_1_PKTDMA_1 Navigator interrupt for Packet DMA starvation
179 QMSS_INTD_1_HIGH_0 Navigator hi interrupt
180 QMSS_INTD_1_HIGH_1 Navigator hi interrupt
181 QMSS_INTD_1_HIGH_2 Navigator hi interrupt
182 QMSS_INTD_1_HIGH_3 Navigator hi interrupt
183 QMSS_INTD_1_HIGH_4 Navigator hi interrupt
184 QMSS_INTD_1_HIGH_5 Navigator hi interrupt
185 QMSS_INTD_1_HIGH_6 Navigator hi interrupt
186 QMSS_INTD_1_HIGH_7 Navigator hi interrupt
187 QMSS_INTD_1_HIGH_8 Navigator hi interrupt
188 QMSS_INTD_1_HIGH_9 Navigator hi interrupt
189 QMSS_INTD_1_HIGH_10 Navigator hi interrupt
190 QMSS_INTD_1_HIGH_11 Navigator hi interrupt
191 QMSS_INTD_1_HIGH_12 Navigator hi interrupt
192 QMSS_INTD_1_HIGH_13 Navigator hi interrupt
193 QMSS_INTD_1_HIGH_14 Navigator hi interrupt
194 QMSS_INTD_1_HIGH_15 Navigator hi interrupt
195 QMSS_INTD_1_HIGH_16 Navigator hi interrupt
196 QMSS_INTD_1_HIGH_17 Navigator hi interrupt
197 QMSS_INTD_1_HIGH_18 Navigator hi interrupt
198 QMSS_INTD_1_HIGH_19 Navigator hi interrupt
199 QMSS_INTD_1_HIGH_20 Navigator hi interrupt
200 QMSS_INTD_1_HIGH_21 Navigator hi interrupt
201 QMSS_INTD_1_HIGH_22 Navigator hi interrupt
202 QMSS_INTD_1_HIGH_23 Navigator hi interrupt
203 QMSS_INTD_1_HIGH_24 Navigator hi interrupt
204 QMSS_INTD_1_HIGH_25 Navigator hi interrupt
205 QMSS_INTD_1_HIGH_26 Navigator hi interrupt
206 QMSS_INTD_1_HIGH_27 Navigator hi interrupt
207 QMSS_INTD_1_HIGH_28 Navigator hi interrupt
208 QMSS_INTD_1_HIGH_29 Navigator hi interrupt
209 QMSS_INTD_1_HIGH_30 Navigator hi interrupt
210 QMSS_INTD_1_HIGH_31 Navigator hi interrupt
211 QMSS_INTD_1_LOW_0 Navigator interrupt
212 QMSS_INTD_1_LOW_1 Navigator interrupt
213 QMSS_INTD_1_LOW_2 Navigator interrupt
214 QMSS_INTD_1_LOW_3 Navigator interrupt
215 QMSS_INTD_1_LOW_4 Navigator interrupt
216 QMSS_INTD_1_LOW_5 Navigator interrupt
217 QMSS_INTD_1_LOW_6 Navigator interrupt
218 QMSS_INTD_1_LOW_7 Navigator interrupt
219 QMSS_INTD_1_LOW_8 Navigator interrupt
220 QMSS_INTD_1_LOW_9 Navigator interrupt
221 QMSS_INTD_1_LOW_10 Navigator interrupt
222 QMSS_INTD_1_LOW_11 Navigator interrupt
223 QMSS_INTD_1_LOW_12 Navigator interrupt
224 QMSS_INTD_1_LOW_13 Navigator interrupt
225 QMSS_INTD_1_LOW_14 Navigator interrupt
226 QMSS_INTD_1_LOW_15 Navigator interrupt
227 QMSS_INTD_2_PKTDMA_0 Navigator interrupt for Packet DMA starvation
228 QMSS_INTD_2_PKTDMA_1 Navigator interrupt for Packet DMA starvation
229 QMSS_INTD_2_HIGH_0 Navigator second hi interrupt
230 QMSS_INTD_2_HIGH_1 Navigator second hi interrupt
231 QMSS_INTD_2_HIGH_2 Navigator second hi interrupt
232 QMSS_INTD_2_HIGH_3 Navigator second hi interrupt
233 QMSS_INTD_2_HIGH_4 Navigator second hi interrupt
234 QMSS_INTD_2_HIGH_5 Navigator second hi interrupt
235 QMSS_INTD_2_HIGH_6 Navigator second hi interrupt
236 QMSS_INTD_2_HIGH_7 Navigator second hi interrupt
237 QMSS_INTD_2_HIGH_8 Navigator second hi interrupt
238 QMSS_INTD_2_HIGH_9 Navigator second hi interrupt
239 QMSS_INTD_2_HIGH_10 Navigator second hi interrupt
240 QMSS_INTD_2_HIGH_11 Navigator second hi interrupt
241 QMSS_INTD_2_HIGH_12 Navigator second hi interrupt
242 QMSS_INTD_2_HIGH_13 Navigator second hi interrupt
243 QMSS_INTD_2_HIGH_14 Navigator second hi interrupt
244 QMSS_INTD_2_HIGH_15 Navigator second hi interrupt
245 QMSS_INTD_2_HIGH_16 Navigator second hi interrupt
246 QMSS_INTD_2_HIGH_17 Navigator second hi interrupt
247 QMSS_INTD_2_HIGH_18 Navigator second hi interrupt
248 QMSS_INTD_2_HIGH_19 Navigator second hi interrupt
249 QMSS_INTD_2_HIGH_20 Navigator second hi interrupt
250 QMSS_INTD_2_HIGH_21 Navigator second hi interrupt
251 QMSS_INTD_2_HIGH_22 Navigator second hi interrupt
252 QMSS_INTD_2_HIGH_23 Navigator second hi interrupt
253 QMSS_INTD_2_HIGH_24 Navigator second hi interrupt
254 QMSS_INTD_2_HIGH_25 Navigator second hi interrupt
255 QMSS_INTD_2_HIGH_26 Navigator second hi interrupt
256 QMSS_INTD_2_HIGH_27 Navigator second hi interrupt
257 QMSS_INTD_2_HIGH_28 Navigator second hi interrupt
258 QMSS_INTD_2_HIGH_29 Navigator second hi interrupt
259 QMSS_INTD_2_HIGH_30 Navigator second hi interrupt
260 QMSS_INTD_2_HIGH_31 Navigator second hi interrupt
261 QMSS_INTD_2_LOW_0 Navigator second interrupt
262 QMSS_INTD_2_LOW_1 Navigator second interrupt
263 QMSS_INTD_2_LOW_2 Navigator second interrupt
264 QMSS_INTD_2_LOW_3 Navigator second interrupt
265 QMSS_INTD_2_LOW_4 Navigator second interrupt
266 QMSS_INTD_2_LOW_5 Navigator second interrupt
267 QMSS_INTD_2_LOW_6 Navigator second interrupt
268 QMSS_INTD_2_LOW_7 Navigator second interrupt
269 QMSS_INTD_2_LOW_8 Navigator second interrupt
270 QMSS_INTD_2_LOW_9 Navigator second interrupt
271 QMSS_INTD_2_LOW_10 Navigator second interrupt
272 QMSS_INTD_2_LOW_11 Navigator second interrupt
273 QMSS_INTD_2_LOW_12 Navigator second interrupt
274 QMSS_INTD_2_LOW_13 Navigator second interrupt
275 QMSS_INTD_2_LOW_14 Navigator second interrupt
276 QMSS_INTD_2_LOW_15 Navigator second interrupt
277 UART_0_UARTINT UART0 interrupt
278 UART_0_URXEVT UART0 receive event
279 UART_0_UTXEVT UART0 transmit event
280 UART_1_UARTINT UART1 interrupt
281 UART_1_URXEVT UART1 receive event
282 UART_1_UTXEVT UART1 transmit event
283 I2C_0_INT I2C interrupt
284 I2C_0_REVT I2C receive event
285 I2C_0_XEVT I2C transmit event
286 I2C_1_INT I2C interrupt
287 I2C_1_REVT I2C receive event
288 I2C_1_XEVT I2C transmit event
289 I2C_2_INT I2C interrupt
290 I2C_2_REVT I2C receive event
291 I2C_2_XEVT I2C transmit event
292 SPI_0_INT0 SPI interrupt
293 SPI_0_INT1 SPI interrupt
294 SPI_0_XEVT SPI DMA TX event
295 SPI_0_REVT SPI DMA RX event
296 SPI_1_INT0 SPI interrupt
297 SPI_1_INT1 SPI interrupt
298 SPI_1_XEVT SPI DMA TX event
299 SPI_1_REVT SPI DMA RX event
300 SPI_2_INT0 SPI interrupt
301 SPI_2_INT1 SPI interrupt
302 SPI_2_XEVT SPI DMA TX event
303 SPI_2_REVT SPI DMA RX event
304 DBGTBR_DMAINT Debug trace buffer (TBR) DMA event
305 DBGTBR_ACQCOMP Debug trace buffer (TBR) Acquisition has been completed
306 ARM_TBR_DMA ARM trace buffer (TBR) DMA event
307 ARM_TBR_ACQ ARM trace buffer (TBR) Acquisition has been completed
308 NETCP_MDIO_LINK_INT0 Packet Accelerator subsystem MDIO interrupt
309 NETCP_MDIO_LINK_INT1 Packet Accelerator subsystem MDIO interrupt
310 NETCP_MDIO_USER_INT0 Packet Accelerator subsystem MDIO interrupt
311 NETCP_MDIO_USER_INT1 Packet Accelerator subsystem MDIO interrupt
312 NETCP_MISC_INT Packet Accelerator subsystem MDIO interrupt
313 NETCP_PKTDMA_INT0 Packet Accelerator Packet DMA starvation interrupt
314 EDMACC_0_GINT EDMA3CC0 global completion interrupt
315 EDMACC_0_TC_0_INT EDMA3CC0 individual completion interrupt
316 EDMACC_0_TC_1_INT EDMA3CC0 individual completion interrupt
317 EDMACC_0_TC_2_INT EDMA3CC0 individual completion interrupt
318 EDMACC_0_TC_3_INT EDMA3CC0 individual completion interrupt
319 EDMACC_0_TC_4_INT EDMA3CC0 individual completion interrupt
320 EDMACC_0_TC_5_INT EDMA3CC0 individual completion interrupt
321 EDMACC_0_TC_6_INT EDMA3CC0 individual completion interrupt
322 EDMACC_0_TC_7_INT EDMA3CC0 individual completion interrupt
323 EDMACC_1_GINT EDMA3CC1 global completion interrupt
324 EDMACC_1_TC_0_INT EDMA3CC1 individual completion interrupt
325 EDMACC_1_TC_1_INT EDMA3CC1 individual completion interrupt
326 EDMACC_1_TC_2_INT EDMA3CC1 individual completion interrupt
327 EDMACC_1_TC_3_INT EDMA3CC1 individual completion interrupt
328 EDMACC_1_TC_4_INT EDMA3CC1 individual completion interrupt
329 EDMACC_1_TC_5_INT EDMA3CC1 individual completion interrupt
330 EDMACC_1_TC_6_INT EDMA3CC1 individual completion interrupt
331 EDMACC_1_TC_7_INT EDMA3CC1 individual completion interrupt
332 EDMACC_2_GINT EDMA3CC2 global completion interrupt
333 EDMACC_2_TC_0_INT EDMA3CC2 individual completion interrupt
334 EDMACC_2_TC_1_INT EDMA3CC2 individual completion interrupt
335 EDMACC_2_TC_2_INT EDMA3CC2 individual completion interrupt
336 EDMACC_2_TC_3_INT EDMA3CC2 individual completion interrupt
337 EDMACC_2_TC_4_INT EDMA3CC2 individual completion interrupt
338 EDMACC_2_TC_5_INT EDMA3CC2 individual completion interrupt
339 EDMACC_2_TC_6_INT EDMA3CC2 individual completion interrupt
340 EDMACC_2_TC_7_INT EDMA3CC2 individual completion interrupt
341 EDMACC_3_GINT EDMA3CC3 global completion interrupt
342 EDMACC_3_TC_0_INT EDMA3CC3 individual completion interrupt
343 EDMACC_3_TC_1_INT EDMA3CC3 individual completion interrupt
344 EDMACC_3_TC_2_INT EDMA3CC3 individual completion interrupt
345 EDMACC_3_TC_3_INT EDMA3CC3 individual completion interrupt
346 EDMACC_3_TC_4_INT EDMA3CC3 individual completion interrupt
347 EDMACC_3_TC_5_INT EDMA3CC3 individual completion interrupt
348 EDMACC_3_TC_6_INT EDMA3CC3 individual completion interrupt
349 EDMACC_3_TC_7_INT EDMA3CC3 individual completion interrupt
350 EDMACC_4_GINT EDMA3CC4 global completion interrupt
351 EDMACC_4_TC_0_INT EDMA3CC4 individual completion interrupt
352 EDMACC_4_TC_1_INT EDMA3CC4 individual completion interrupt
353 EDMACC_4_TC_2_INT EDMA3CC4 individual completion interrupt
354 EDMACC_4_TC_3_INT EDMA3CC4 individual completion interrupt
355 EDMACC_4_TC_4_INT EDMA3CC4 individual completion interrupt
356 EDMACC_4_TC_5_INT EDMA3CC4 individual completion interrupt
357 EDMACC_4_TC_6_INT EDMA3CC4 individual completion interrupt
358 EDMACC_4_TC_7_INT EDMA3CC4 individual completion interrupt
359 SR_0_PO_VCON_SMPSERR_INT SmartReflex SMPS Error interrupt
360 SR_0_SMARTREFLEX_INTREQ0 SmartReflex controller interrupt
361 SR_0_SMARTREFLEX_INTREQ1 SmartReflex controller interrupt
362 SR_0_SMARTREFLEX_INTREQ2 SmartReflex controller interrupt
363 SR_0_SMARTREFLEX_INTREQ3 SmartReflex controller interrupt
364 SR_0_VPNOSMPSACK SmartReflex VPVOLTUPDATE has been asserted but SMPS has not been responded to in a defined time interval
365 SR_0_VPEQVALUE SmartReflex SRSINTERUPT is asserted, but the new voltage is not different from the current SMPS voltage
366 SR_0_VPMAXVDD SmartReflex The new voltage required is equal to or greater than MaxVdd
367 SR_0_VPMINVDD SmartReflex The new voltage required is equal to or less than MinVdd
368 SR_0_VPINIDLE SmartReflex. Indicating that the FSM of voltage processor is in idle
369 SR_0_VPOPPCHANGEDONE SmartReflex Indicating that the average frequency error is within the desired limit
370 SR_0_VPSMPSACK SmartReflex VPVOLTUPDATE asserted and SMPS has acknowledged in a defined time interval
371 SR_0_SR_TEMPSENSOR SmartReflex temperature threshold crossing interrupt
372 SR_0_SR_TIMERINT SmartReflex internal timer expiration interrupt
373 SR_1_PO_VCON_SMPSERR_INT SmartReflex SMPS Error interrupt
374 SR_1_SMARTREFLEX_INTREQ0 SmartReflex controller interrupt
375 SR_1_SMARTREFLEX_INTREQ1 SmartReflex controller interrupt
376 SR_1_SMARTREFLEX_INTREQ2 SmartReflex controller interrupt
377 SR_1_SMARTREFLEX_INTREQ3 SmartReflex controller interrupt
378 SR_1_VPNOSMPSACK SmartReflex VPVOLTUPDATE has been asserted but SMPS has not been responded to in a defined time interval
379 SR_1_VPEQVALUE SmartReflex SRSINTERUPT is asserted, but the new voltage is not different from the current SMPS voltage
380 SR_1_VPMAXVDD SmartReflex The new voltage required is equal to or greater than MaxVdd
381 SR_1_VPMINVDD SmartReflex The new voltage required is equal to or less than MinVdd
382 SR_1_VPINIDLE SmartReflex. Indicating that the FSM of voltage processor is in idle
383 SR_1_VPOPPCHANGEDONE SmartReflex Indicating that the average frequency error is within the desired limit
384 SR_1_VPSMPSACK SmartReflex VPVOLTUPDATE asserted and SMPS has acknowledged in a defined time interval
385 SR_1_SR_TEMPSENSOR SmartReflex temperature threshold crossing interrupt
386 SR_1_SR_TIMERINT SmartReflex internal timer expiration interrupt
387 HyperLink_0_INT HyperLink 0 interrupt
388 HyperLink_1_INT HyperLink 1 interrupt
389 ARM_NCTIIRQ0 ARM cross trigger (CTI) IRQ interrupt
390 ARM_NCTIIRQ1 ARM cross trigger (CTI) IRQ interrupt
391 ARM_NCTIIRQ2 ARM cross trigger (CTI) IRQ interrupt
392 ARM_NCTIIRQ3 ARM cross trigger (CTI) IRQ interrupt
393 USB_INT00 USB event ring 0 interrupt
394 USB_INT01 USB event ring 1 interrupt
395 USB_INT02 USB event ring 2 interrupt
396 USB_INT03 USB event ring 3 interrupt
397 USB_INT04 USB event ring 4 interrupt
398 USB_OABSINT USB OABS interrupt
399 USB_MISCINT USB miscellaneous interrupt
400 Reserved Reserved
401 Reserved Reserved
402 10GbE_LINK_INT0 10 Gigabit Ethernet subsystem MDIO interrupt (66AK2H14 only)
403 10GbE_USER_INT0 10 Gigabit Ethernet subsystem MDIO interrupt (66AK2H14 only)
404 10GbE_LINK_INT1 10 Gigabit Ethernet subsystem MDIO interrupt (66AK2H14 only)
405 10GbE_USER_INT1 10 Gigabit Ethernet subsystem MDIO interrupt (66AK2H14 only)
406 10GbE_MISC_INT 10 Gigabit Ethernet subsystem MDIO interrupt (66AK2H14 only)
407 10GbE_INT_PKTDMA_0 10 Gigabit Ethernet Packet DMA starvation interrupt (66AK2H14 only)
408 Reserved Reserved
409 Reserved Reserved
410 Reserved Reserved
411 Reserved Reserved
412 Reserved Reserved
413 Reserved Reserved
414 Reserved Reserved
415 Reserved Reserved
416 Reserved Reserved
417 Reserved Reserved
418 Reserved Reserved
419 Reserved Reserved
420 Reserved Reserved
421 Reserved Reserved
422 Reserved Reserved
423 Reserved Reserved
424 Reserved Reserved
425 Reserved Reserved
426 Reserved Reserved
427 Reserved Reserved
428 Reserved Reserved
429 Reserved Reserved
430 Reserved Reserved
431 Reserved Reserved
432 Reserved Reserved
433 Reserved Reserved
434 Reserved Reserved
435 Reserved Reserved
436 Reserved Reserved
437 Reserved Reserved
438 Reserved Reserved
439 Reserved Reserved
440 Reserved Reserved
441 Reserved Reserved
442 Reserved Reserved
443 Reserved Reserved
444 Reserved Reserved
445 Reserved Reserved
446 Reserved Reserved
447 Reserved Reserved
448 CIC_2_OUT29 CIC2 interrupt
449 CIC_2_OUT30 CIC2 interrupt
450 CIC_2_OUT31 CIC2 interrupt
451 CIC_2_OUT32 CIC2 interrupt
452 CIC_2_OUT33 CIC2 interrupt
453 CIC_2_OUT34 CIC2 interrupt
454 CIC_2_OUT35 CIC2 interrupt
455 CIC_2_OUT36 CIC2 interrupt
456 CIC_2_OUT37 CIC2 interrupt
457 CIC_2_OUT38 CIC2 interrupt
458 CIC_2_OUT39 CIC2 interrupt
459 CIC_2_OUT40 CIC2 interrupt
460 CIC_2_OUT41 CIC2 interrupt
461 CIC_2_OUT42 CIC2 interrupt
462 CIC_2_OUT43 CIC2 interrupt
463 CIC_2_OUT44 CIC2 interrupt
464 CIC_2_OUT45 CIC2 interrupt
465 CIC_2_OUT46 CIC2 interrupt
466 CIC_2_OUT47 CIC2 interrupt
467 CIC_2_OUT18 CIC2 interrupt
468 CIC_2_OUT19 CIC2 interrupt
469 CIC_2_OUT22 CIC2 interrupt
470 CIC_2_OUT23 CIC2 interrupt
471 CIC_2_OUT50 CIC2 interrupt
472 CIC_2_OUT51 CIC2 interrupt
473 CIC_2_OUT66 CIC2 interrupt
474 CIC_2_OUT67 CIC2 interrupt
475 CIC_2_OUT88 CIC2 interrupt
476 CIC_2_OUT89 CIC2 interrupt
477 CIC_2_OUT90 CIC2 interrupt
478 CIC_2_OUT91 CIC2 interrupt
479 CIC_2_OUT92 CIC2 interrupt
(1) 66AK2H12/14 only.

Table 8-24, Table 8-25, and Table 8-26 list the C66x CorePac Secondary interrupt inputs.

Table 8-24 CIC0 Event Inputs — C66x CorePac Secondary Interrupts

EVENT NO. EVENT NAME DESCRIPTION
0 EDMACC_1_ERRINT EDMA3CC1 error interrupt
1 EDMACC_1_MPINT EDMA3CC1 memory protection interrupt
2 EDMACC_1_TC_0_ERRINT EDMA3CC1 TPTC0 error interrupt
3 EDMACC_1_TC_1_ERRINT EDMA3CC1 TPTC1 error interrupt
4 EDMACC_1_TC_2_ERRINT EDMA3CC1 TPTC2 error interrupt
5 EDMACC_1_TC_3_ERRINT EDMA3CC1 TPTC3 error interrupt
6 EDMACC_1_GINT EDMA3CC1 GINT
7 Reserved Reserved
8 EDMACC_1_TC_0_INT EDMA3CC1 individual completion interrupt
9 EDMACC_1_TC_1_INT EDMA3CC1 individual completion interrupt
10 EDMACC_1_TC_2_INT EDMA3CC1 individual completion interrupt
11 EDMACC_1_TC_3_INT EDMA3CC1 individual completion interrupt
12 EDMACC_1_TC_4_INT EDMA3CC1 individual completion interrupt
13 EDMACC_1_TC_5_INT EDMA3CC1 individual completion interrupt
14 EDMACC_1_TC_6_INT EDMA3CC1 individual completion interrupt
15 EDMACC_1_TC_7_INT EDMA3CC1 individual completion interrupt
16 EDMACC_2_ERRINT EDMA3CC2 error interrupt
17 EDMACC_2_MPINT EDMA3CC2 memory protection interrupt
18 EDMACC_2_TC_0_ERRINT EDMA3CC2 TPTC0 error interrupt
19 EDMACC_2_TC_1_ERRINT EDMA3CC2 TPTC1 error interrupt
20 EDMACC_2_TC_2_ERRINT EDMA3CC2 TPTC2 error interrupt
21 EDMACC_2_TC_3_ERRINT EDMA3CC2 TPTC3 error interrupt
22 EDMACC_2_GINT EDMA3CC2 GINT
23 Reserved Reserved
24 EDMACC_2_TC_0_INT EDMA3CC2 individual completion interrupt
25 EDMACC_2_TC_1_INT EDMA3CC2 individual completion interrupt
26 EDMACC_2_TC_2_INT EDMA3CC2 individual completion interrupt
27 EDMACC_2_TC_3_INT EDMA3CC2 individual completion interrupt
28 EDMACC_2_TC_4_INT EDMA3CC2 individual completion interrupt
29 EDMACC_2_TC_5_INT EDMA3CC2 individual completion interrupt
30 EDMACC_2_TC_6_INT EDMA3CC2 individual completion interrupt
31 EDMACC_2_TC_7_INT EDMA3CC2 individual completion interrupt
32 EDMACC_0_ERRINT EDMA3CC0 error interrupt
33 EDMACC_0_MPINT EDMA3CC0 memory protection interrupt
34 EDMACC_0_TC_0_ERRINT EDMA3CC0 TPTC0 error interrupt
35 EDMACC_0_TC_1_ERRINT EDMA3CC0 TPTC1 error interrupt
36 EDMACC_0_GINT EDMA3CC0 global completion interrupt
37 Reserved Reserved
38 EDMACC_0_TC_0_INT EDMA3CC0 individual completion interrupt
39 EDMACC_0_TC_1_INT EDMA3CC0 individual completion interrupt
40 EDMACC_0_TC_2_INT EDMA3CC0 individual completion interrupt
41 EDMACC_0_TC_3_INT EDMA3CC0 individual completion interrupt
42 EDMACC_0_TC_4_INT EDMA3CC0 individual completion interrupt
43 EDMACC_0_TC_5_INT EDMA3CC0 individual completion interrupt
44 EDMACC_0_TC_6_INT EDMA3CC0 individual completion interrupt
45 EDMACC_0_TC_7_INT EDMA3CC0 individual completion interrupt
46 Reserved Reserved
47 QMSS_QUE_PEND_652 Navigator transmit queue pending event for indicated queue
48 PCIE_INT12 PCIE protocol error interrupt
49 PCIE_INT13 PCIE power management interrupt
50 PCIE_INT0 PCIE legacy INTA interrupt
51 PCIE_INT1 PCIE legacy INTB interrupt
52 PCIE_INT2 PCIE legacy INTC interrupt
53 PCIE_INT3 PCIE legacy INTD interrupt
54 SPI_0_INT0 SPI0 interrupt0
55 SPI_0_INT1 SPI0 interrupt1
56 SPI_0_XEVT SPI0 transmit event
57 SPI_0_REVT SPI0 receive event
58 I2C_0_INT I2C0 interrupt
59 I2C_0_REVT I2C0 receive event
60 I2C_0_XEVT I2C0 transmit event
61 Reserved Reserved
62 Reserved Reserved
63 DBGTBR_DMAINT Debug trace buffer (TBR) DMA event
64 MPU_12_INT MPU12 addressing violation interrupt and protection violation interrupt
65 DBGTBR_ACQCOMP Debug trace buffer (TBR) acquisition has been completed
66 MPU_13_INT MPU13 addressing violation interrupt and protection violation interrupt
67 MPU_14_INT MPU14 addressing violation interrupt and protection violation interrupt
68 NETCP_MDIO_LINK_INT0 Packet Accelerator 0 subsystem MDIO interrupt
69 NETCP_MDIO_LINK_INT1 Packet Accelerator 0 subsystem MDIO interrupt
70 NETCP_MDIO_USER_INT0 Packet Accelerator 0 subsystem MDIO interrupt
71 NETCP_MDIO_USER_INT1 Packet Accelerator 0 subsystem MDIO interrupt
72 NETCP_MISC_INT Packet Accelerator 0 subsystem misc interrupt
73 TRACER_CORE_0_INT Tracer sliding time window interrupt for DSP0 L2
74 TRACER_CORE_1_INT Tracer sliding time window interrupt for DSP1 L2
75 TRACER_CORE_2_INT Tracer sliding time window interrupt for DSP2 L2
76 TRACER_CORE_3_INT Tracer sliding time window interrupt for DSP3 L2
77 TRACER_DDR_INT Tracer sliding time window interrupt for MSMC-DDR3A
78 TRACER_MSMC_0_INT Tracer sliding time window interrupt for MSMC SRAM bank0
79 TRACER_MSMC_1_INT Tracer sliding time window interrupt for MSMC SRAM bank1
80 TRACER_MSMC_2_INT Tracer sliding time window interrupt for MSMC SRAM bank2
81 TRACER_MSMC_3_INT Tracer sliding time window interrupt for MSMC SRAM bank3
82 TRACER_CFG_INT Tracer sliding time window interrupt for CFG0 TeraNet
83 TRACER_QMSS_QM_CFG1_INT Tracer sliding time window interrupt for Navigator CFG1 slave port
84 TRACER_QMSS_DMA_INT Tracer sliding time window interrupt for Navigator DMA internal bus slave port
85 TRACER_SEM_INT Tracer sliding time window interrupt for Semaphore
86 PSC_ALLINT Power & Sleep Controller interrupt
87 MSMC_SCRUB_CERROR Correctable (1-bit) soft error detected during scrub cycle
88 BOOTCFG_INT Chip-level MMR Error Register
89 SR_0_PO_VCON_SMPSERR_INT SmartReflex SMPS error interrupt
90 MPU_0_INT MPU0 addressing violation interrupt and protection violation interrupt
91 QMSS_QUE_PEND_653 Navigator transmit queue pending event for indicated queue
92 MPU_1_INT MPU1 addressing violation interrupt and protection violation interrupt.
93 QMSS_QUE_PEND_654 Navigator transmit queue pending event for indicated queue
94 MPU_2_INT MPU2 addressing violation interrupt and protection violation interrupt.
95 QMSS_QUE_PEND_655 Navigator transmit queue pending event for indicated queue
96 MPU_3_INT MPU3 addressing violation interrupt and protection violation interrupt.
97 QMSS_QUE_PEND_656 Navigator transmit queue pending event for indicated queue
98 MSMC_DEDC_CERROR Correctable (1-bit) soft error detected on SRAM read
99 MSMC_DEDC_NC_ERROR Noncorrectable (2-bit) soft error detected on SRAM read
100 MSMC_SCRUB_NC_ERROR Noncorrectable (2-bit) soft error detected during scrub cycle
101 MSMC_MPF_ERROR0 Memory protection fault indicators for system master PrivID = 0
102 MSMC_MPF_ERROR8 Memory protection fault indicators for system master PrivID = 8
103 MSMC_MPF_ERROR9 Memory protection fault indicators for system master PrivID = 9
104 MSMC_MPF_ERROR10 Memory protection fault indicators for system master PrivID = 10
105 MSMC_MPF_ERROR11 Memory protection fault indicators for system master PrivID = 11
106 MSMC_MPF_ERROR12 Memory protection fault indicators for system master PrivID = 12
107 MSMC_MPF_ERROR13 Memory protection fault indicators for system master PrivID = 13
108 MSMC_MPF_ERROR14 Memory protection fault indicators for system master PrivID = 14
109 MSMC_MPF_ERROR15 Memory protection fault indicators for system master PrivID = 15
110 DDR3_0_ERR DDR3A_EMIF error interrupt
111 HYPERLINK_0_INT HyperLink 0 interrupt
112 SRIO_INTDST0 SRIO interrupt
113 SRIO_INTDST1 SRIO interrupt
114 SRIO_INTDST2 SRIO interrupt
115 SRIO_INTDST3 SRIO interrupt
116 SRIO_INTDST4 SRIO interrupt
117 SRIO_INTDST5 SRIO interrupt
118 SRIO_INTDST6 SRIO interrupt
119 SRIO_INTDST7 SRIO interrupt
120 SRIO_INTDST8 SRIO interrupt
121 SRIO_INTDST9 SRIO interrupt
122 SRIO_INTDST10 SRIO interrupt
123 SRIO_INTDST11 SRIO interrupt
124 SRIO_INTDST12 SRIO interrupt
125 SRIO_INTDST13 SRIO interrupt
126 SRIO_INTDST14 SRIO interrupt
127 SRIO_INTDST15 SRIO interrupt
128 AEMIF_EASYNCERR Asynchronous EMIF16 error interrupt
129 TRACER_CORE_4_INT Tracer sliding time window interrupt for DSP4 L2
130 TRACER_CORE_5_INT Tracer sliding time window interrupt for DSP5 L2
131 TRACER_CORE_6_INT Tracer sliding time window interrupt for DSP6 L2
132 TRACER_CORE_7_INT Tracer sliding time window interrupt for DSP7 L2
133 QMSS_INTD_1_PKTDMA_0 Navigator interrupt for Packet DMA starvation
134 QMSS_INTD_1_PKTDMA_1 Navigator interrupt for Packet DMA starvation
135 SRIO_INT_PKTDMA_0 IPC interrupt generation
136 NETCP_PKTDMA_INT0 Packet Accelerator0 Packet DMA starvation interrupt
137 SR_0_SMARTREFLEX_INTREQ0 SmartReflex controller interrupt
138 SR_0_SMARTREFLEX_INTREQ1 SmartReflex controller interrupt
139 SR_0_SMARTREFLEX_INTREQ2 SmartReflex controller interrupt
140 SR_0_SMARTREFLEX_INTREQ3 SmartReflex controller interrupt
141 SR_0_VPNOSMPSACK SmartReflex VPVOLTUPDATE has been asserted but SMPS has not been responded to in a defined time interval
142 SR_0_VPEQVALUE SmartReflex SRSINTERUPT is asserted, but the new voltage is not different from the current SMPS voltage
143 SR_0_VPMAXVDD SmartReflex. The new voltage required is equal to or greater than MaxVdd
144 SR_0_VPMINVDD SmartReflex. The new voltage required is equal to or less than MinVdd
145 SR_0_VPINIDLE SmartReflex indicating that the FSM of voltage processor is in idle
146 SR_0_VPOPPCHANGEDONE SmartReflex indicating that the average frequency error is within the desired limit
147 Reserved Reserved
148 UART_0_UARTINT UART0 interrupt
149 UART_0_URXEVT UART0 receive event
150 UART_0_UTXEVT UART0 transmit event
151 QMSS_QUE_PEND_657 Navigator transmit queue pending event for indicated queue
152 QMSS_QUE_PEND_658 Navigator transmit queue pending event for indicated queue
153 QMSS_QUE_PEND_659 Navigator transmit queue pending event for indicated queue
154 QMSS_QUE_PEND_660 Navigator transmit queue pending event for indicated queue
155 QMSS_QUE_PEND_661 Navigator transmit queue pending event for indicated queue
156 QMSS_QUE_PEND_662 Navigator transmit queue pending event for indicated queue
157 QMSS_QUE_PEND_663 Navigator transmit queue pending event for indicated queue
158 QMSS_QUE_PEND_664 Navigator transmit queue pending event for indicated queue
159 QMSS_QUE_PEND_665 Navigator transmit queue pending event for indicated queue
160 SR_0_VPSMPSACK SmartReflex VPVOLTUPDATE asserted and SMPS has acknowledged in a defined time interval
161 ARM_TBR_DMA ARM trace buffer (TBR) DMA event
162 ARM_TBR_ACQ ARM trace buffer (TBR) acquisition has been completed
163 ARM_NINTERRIRQ ARM internal memory ECC error interrupt request
164 ARM_NAXIERRIRQ ARM bus error interrupt request
165 SR_0_SR_TEMPSENSOR SmartReflex temperature threshold crossing interrupt
166 SR_0_SR_TIMERINT SmartReflex internal timer expiration interrupt
167 Reserved Reserved
168 Reserved Reserved
169 Reserved Reserved
170 Reserved Reserved
171 Reserved Reserved
172 Reserved Reserved
173 Reserved Reserved
174 Reserved Reserved
175 TIMER_7_INTL Timer interrupt low(1)
176 TIMER_7_INTH Timer interrupt high(1)
177 TIMER_6_INTL Timer interrupt low(1)
178 TIMER_6_INTH Timer interrupt high(1)
179 TIMER_5_INTL Timer interrupt low(1)
180 TIMER_5_INTH Timer interrupt high(1)
181 TIMER_4_INTL Timer interrupt low(1)
182 TIMER_4_INTH Timer interrupt high(1)
183 TIMER_3_INTL Timer interrupt low
184 TIMER_3_INTH Timer interrupt high
185 TIMER_2_INTL Timer interrupt low
186 TIMER_2_INTH Timer interrupt high
187 TIMER_1_INTL Timer interrupt low
188 TIMER_1_INTH Timer interrupt high
189 TIMER_0_INTL Timer interrupt low
190 TIMER_0_INTH Timer interrupt high
191 Reserved Reserved
192 Reserved Reserved
193 Reserved Reserved
194 Reserved Reserved
195 Reserved Reserved
196 Reserved Reserved
197 Reserved Reserved
198 Reserved Reserved
199 Reserved Reserved
200 Reserved Reserved
201 Reserved Reserved
202 Reserved Reserved
203 Reserved Reserved
204 Reserved Reserved
205 Reserved Reserved
206 Reserved Reserved
207 EDMACC_4_ERRINT EDMA3CC4 error interrupt
208 EDMACC_4_MPINT EDMA3CC4 memory protection interrupt
209 EDMACC_4_TC_0_ERRINT EDMA3CC4 TPTC0 error interrupt
210 EDMACC_4_TC_1_ERRINT EDMA3CC4 TPTC1 error interrupt
211 EDMACC_4_GINT EDMA3CC4 GINT
212 EDMACC_4_TC_0_INT EDMA3CC4 individual completion interrupt
213 EDMACC_4_TC_1_INT EDMA3CC4 individual completion interrupt
214 EDMACC_4_TC_2_INT EDMA3CC4 individual completion interrupt
215 EDMACC_4_TC_3_INT EDMA3CC4 individual completion interrupt
216 EDMACC_4_TC_4_INT EDMA3CC4 individual completion interrupt
217 EDMACC_4_TC_5_INT EDMA3CC4 individual completion interrupt
218 EDMACC_4_TC_6_INT EDMA3CC4 individual completion interrupt
219 EDMACC_4_TC_7_INT EDMA3CC4 individual completion interrupt
220 EDMACC_3_ERRINT EDMA3CC3 error interrupt
221 EDMACC_3_MPINT EDMA3CC3 memory protection interrupt
222 EDMACC_3_TC_0_ERRINT EDMA3CC3 TPTC0 error interrupt
223 EDMACC_3_TC_1_ERRINT EDMA3CC3 TPTC1 error interrupt
224 EDMACC_3_GINT EDMA3CC3 GINT
225 EDMACC_3_TC_0_INT EDMA3CC3 individual completion interrupt
226 EDMACC_3_TC_1_INT EDMA3CC3 individual completion interrupt
227 EDMACC_3_TC_2_INT EDMA3CC3 individual completion interrupt
228 EDMACC_3_TC_3_INT EDMA3CC3 individual completion interrupt
229 EDMACC_3_TC_4_INT EDMA3CC3 individual completion interrupt
230 EDMACC_3_TC_5_INT EDMA3CC3 individual completion interrupt
231 EDMACC_3_TC_6_INT EDMA3CC3 individual completion interrupt
232 EDMACC_3_TC_7_INT EDMA3CC3 individual completion interrupt
233 UART_1_UARTINT UART1 interrupt
234 UART_1_URXEVT UART1 receive event
235 UART_1_UTXEVT UART1 transmit event
236 I2C_1_INT I2C1 interrupt
237 I2C_1_REVT I2C1 receive event
238 I2C_1_XEVT I2C1 transmit event
239 SPI_1_INT0 SPI1 interrupt0
240 SPI_1_INT1 SPI1 interrupt1
241 SPI_1_XEVT SPI1 transmit event
242 SPI_1_REVT SPI1 receive event
243 MPU_5_INT MPU5 addressing violation interrupt and protection violation interrupt
244 MPU_8_INT MPU8 addressing violation interrupt and protection violation interrupt
245 MPU_9_INT MPU9 addressing violation interrupt and protection violation interrupt
246 MPU_11_INT MPU11 addressing violation interrupt and protection violation interrupt
247 MPU_4_INT MPU4 addressing violation interrupt and protection violation interrupt
248 MPU_6_INT MPU6 addressing violation interrupt and protection violation interrupt
249 MPU_7_INT MPU7 addressing violation interrupt and protection violation interrupt
250 MPU_10_INT MPU10 addressing violation interrupt and protection violation interrupt
251 SPI_2_INT0 SPI2 interrupt0
252 SPI_2_INT1 SPI2 interrupt1
253 SPI_2_XEVT SPI2 transmit event
254 SPI_2_REVT SPI2 receive event
255 I2C_2_INT I2C2 interrupt
256 I2C_2_REVT I2C2 receive event
257 I2C_2_XEVT I2C2 transmit event
258 Reserved Reserved
259 Reserved Reserved
260 Reserved Reserved
261 Reserved Reserved
262 Reserved Reserved
263 Reserved Reserved
264 Reserved Reserved
265 Reserved Reserved
266 Reserved Reserved
267 Reserved Reserved
268 Reserved Reserved
269 Reserved Reserved
270 Reserved Reserved
271 Reserved Reserved
272 Reserved Reserved
273 Reserved Reserved
274 Reserved Reserved
275 Reserved Reserved
276 Reserved Reserved
277 Reserved Reserved
278 Reserved Reserved
279 Reserved Reserved
280 Reserved Reserved
281 Reserved Reserved
282 Reserved Reserved
283 Reserved Reserved
284 Reserved Reserved
285 Reserved Reserved
286 Reserved Reserved
287 Reserved Reserved
288 Reserved Reserved
289 Reserved Reserved
290 Reserved Reserved
291 Reserved Reserved
292 QMSS_QUE_PEND_666 Navigator transmit queue pending event for indicated queue
293 QMSS_QUE_PEND_667 Navigator transmit queue pending event for indicated queue
294 QMSS_QUE_PEND_668 Navigator transmit queue pending event for indicated queue
295 QMSS_QUE_PEND_669 Navigator transmit queue pending event for indicated queue
296 QMSS_QUE_PEND_670 Navigator transmit queue pending event for indicated queue
297 QMSS_QUE_PEND_671 Navigator transmit queue pending event for indicated queue
298 QMSS_QUE_PEND_8844 Navigator transmit queue pending event for indicated queue
299 QMSS_QUE_PEND_8845 Navigator transmit queue pending event for indicated queue
300 QMSS_QUE_PEND_8846 Navigator transmit queue pending event for indicated queue
301 QMSS_QUE_PEND_8847 Navigator transmit queue pending event for indicated queue
302 QMSS_QUE_PEND_8848 Navigator transmit queue pending event for indicated queue
303 QMSS_QUE_PEND_8849 Navigator transmit queue pending event for indicated queue
304 QMSS_QUE_PEND_8850 Navigator transmit queue pending event for indicated queue
305 QMSS_QUE_PEND_8851 Navigator transmit queue pending event for indicated queue
306 QMSS_QUE_PEND_8852 Navigator transmit queue pending event for indicated queue
307 QMSS_QUE_PEND_8853 Navigator transmit queue pending event for indicated queue
308 QMSS_QUE_PEND_8854 Navigator transmit queue pending event for indicated queue
309 QMSS_QUE_PEND_8855 Navigator transmit queue pending event for indicated queue
310 QMSS_QUE_PEND_8856 Navigator transmit queue pending event for indicated queue
311 QMSS_QUE_PEND_8857 Navigator transmit queue pending event for indicated queue
312 QMSS_QUE_PEND_8858 Navigator transmit queue pending event for indicated queue
313 QMSS_QUE_PEND_8859 Navigator transmit queue pending event for indicated queue
314 QMSS_QUE_PEND_8860 Navigator transmit queue pending event for indicated queue
315 QMSS_QUE_PEND_8861 Navigator transmit queue pending event for indicated queue
316 QMSS_QUE_PEND_8862 Navigator transmit queue pending event for indicated queue
317 QMSS_QUE_PEND_8863 Navigator transmit queue pending event for indicated queue
318 QMSS_INTD_2_PKTDMA_0 Navigator ECC error interrupt
319 QMSS_INTD_2_PKTDMA_1 Navigator ECC error interrupt
320 QMSS_INTD_1_LOW_0 Navigator interrupt low
321 QMSS_INTD_1_LOW_1 Navigator interrupt low
322 QMSS_INTD_1_LOW_2 Navigator interrupt low
323 QMSS_INTD_1_LOW_3 Navigator interrupt low
324 QMSS_INTD_1_LOW_4 Navigator interrupt low
325 QMSS_INTD_1_LOW_5 Navigator interrupt low
326 QMSS_INTD_1_LOW_6 Navigator interrupt low
327 QMSS_INTD_1_LOW_7 Navigator interrupt low
328 QMSS_INTD_1_LOW_8 Navigator interrupt low
329 QMSS_INTD_1_LOW_9 Navigator interrupt low
330 QMSS_INTD_1_LOW_10 Navigator interrupt low
331 QMSS_INTD_1_LOW_11 Navigator interrupt low
332 QMSS_INTD_1_LOW_12 Navigator interrupt low
333 QMSS_INTD_1_LOW_13 Navigator interrupt low
334 QMSS_INTD_1_LOW_14 Navigator interrupt low
335 QMSS_INTD_1_LOW_15 Navigator interrupt low
336 QMSS_INTD_2_LOW_0 Navigator second interrupt low
337 QMSS_INTD_2_LOW_1 Navigator second interrupt low
338 QMSS_INTD_2_LOW_2 Navigator second interrupt low
339 QMSS_INTD_2_LOW_3 Navigator second interrupt low
340 QMSS_INTD_2_LOW_4 Navigator second interrupt low
341 QMSS_INTD_2_LOW_5 Navigator second interrupt low
342 QMSS_INTD_2_LOW_6 Navigator second interrupt low
343 QMSS_INTD_2_LOW_7 Navigator second interrupt low
344 QMSS_INTD_2_LOW_8 Navigator second interrupt low
345 QMSS_INTD_2_LOW_9 Navigator second interrupt low
346 QMSS_INTD_2_LOW_10 Navigator second interrupt low
347 QMSS_INTD_2_LOW_11 Navigator second interrupt low
348 QMSS_INTD_2_LOW_12 Navigator second interrupt low
349 QMSS_INTD_2_LOW_13 Navigator second interrupt low
350 QMSS_INTD_2_LOW_14 Navigator second interrupt low
351 QMSS_INTD_2_LOW_15 Navigator second interrupt low
352 TRACER_EDMACC_0 Tracer sliding time window interrupt for EDMA3CC0
353 TRACER_EDMACC_123_INT Tracer sliding time window interrupt for EDMA3CC1, EDMA3CC2 and EDMA3CC3
354 TRACER_CIC_INT Tracer sliding time window interrupt for interrupt controllers (CIC)
355 TRACER_MSMC_4_INT Tracer sliding time window interrupt for MSMC SRAM bank4
356 TRACER_MSMC_5_INT Tracer sliding time window interrupt for MSMC SRAM bank5
357 TRACER_MSMC_6_INT Tracer sliding time window interrupt for MSMC SRAM bank6
358 TRACER_MSMC_7_INT Tracer sliding time window interrupt for MSMC SRAM bank7
359 TRACER_SPI_ROM_EMIF_INT Tracer sliding time window interrupt for SPI/ROM/EMIF16 modules
360 TRACER_QMSS_QM_CFG2_INT Tracer sliding time window interrupt for QM2
361 Reserved Reserved
362 Reserved Reserved
363 TRACER_DDR_1_INT Tracer sliding time window interrupt for DDR3B
364 Reserved Reserved
365 HYPERLINK_1_INT HyperLink 1 interrupt
366 Reserved Reserved
367 Reserved Reserved
368 Reserved Reserved
369 Reserved Reserved
370 Reserved Reserved
371 Reserved Reserved
372 Reserved Reserved
373 Reserved Reserved
374 Reserved Reserved
375 Reserved Reserved
376 Reserved Reserved
377 Reserved Reserved
378 Reserved Reserved
379 Reserved Reserved
380 Reserved Reserved
381 Reserved Reserved
382 Reserved Reserved
383 Reserved Reserved
384 Reserved Reserved
385 Reserved Reserved
386 Reserved Reserved
387 Reserved Reserved
388 Reserved Reserved
389 Reserved Reserved
390 Reserved Reserved
391 Reserved Reserved
392 Reserved Reserved
393 Reserved Reserved
394 Reserved Reserved
395 Reserved Reserved
396 Reserved Reserved
397 Reserved Reserved
398 Reserved Reserved
399 Reserved Reserved
400 Reserved Reserved
401 Reserved Reserved
402 Reserved Reserved
403 Reserved Reserved
404 Reserved Reserved
405 Reserved Reserved
406 Reserved Reserved
407 Reserved Reserved
408 Reserved Reserved
409 Reserved Reserved
410 Reserved Reserved
411 Reserved Reserved
412 Reserved Reserved
413 Reserved Reserved
414 Reserved Reserved
415 Reserved Reserved
416 Reserved Reserved
417 Reserved Reserved
418 Reserved Reserved
419 Reserved Reserved
420 Reserved Reserved
421 Reserved Reserved
422 USB_INT00 USB interrupt
423 USB_INT04 USB interrupt
424 USB_INT05 USB interrupt
425 USB_INT06 USB interrupt
426 USB_INT07 USB interrupt
427 USB_INT08 USB interrupt
428 USB_INT09 USB interrupt
429 USB_INT10 USB interrupt
430 USB_INT11 USB interrupt
431 USB_MISCINT USB miscellaneous interrupt
432 USB_OABSINT USB OABS interrupt
433 TIMER_12_INTL Timer interrupt low
434 TIMER_12_INTH Timer interrupt high
435 TIMER_13_INTL Timer interrupt low
436 TIMER_13_INTH Timer interrupt high
437 TIMER_14_INTL Timer interrupt low
438 TIMER_14_INTH Timer interrupt high
439 TIMER_15_INTL Timer interrupt low
440 TIMER_15_INTH Timer interrupt high
441 TIMER_16_INTL Timer interrupt low
442 TIMER_17_INTL Timer interrupt high
443 TIMER_18_INTL Timer interrupt low(1)
444 TIMER_19_INTL Timer interrupt high(1)
445 DDR3_1_ERR DDR3B_EMIF error interrupt
446 GPIO_INT16 GPIO interrupt
447 GPIO_INT17 GPIO interrupt
448 GPIO_INT18 GPIO interrupt
449 GPIO_INT19 GPIO interrupt
450 GPIO_INT20 GPIO interrupt
451 GPIO_INT21 GPIO interrupt
452 GPIO_INT22 GPIO interrupt
453 GPIO_INT23 GPIO interrupt
454 GPIO_INT24 GPIO interrupt
455 GPIO_INT25 GPIO interrupt
456 GPIO_INT26 GPIO interrupt
457 GPIO_INT27 GPIO interrupt
458 GPIO_INT28 GPIO interrupt
459 GPIO_INT29 GPIO interrupt
460 GPIO_INT30 GPIO interrupt
461 GPIO_INT31 GPIO interrupt
462 SRIO_INTDST16 SRIOI interrupt
463 SRIO_INTDST17 SRIOI interrupt
464 SRIO_INTDST18 SRIOI interrupt
465 SRIO_INTDST19 SRIOI interrupt
466 PCIE_INT4 PCIE MSI interrupt
467 PCIE_INT5 PCIE MSI interrupt
468 PCIE_INT6 PCIE MSI interrupt
469 PCIE_INT7 PCIE MSI interrupt
470 SEM_INT12 Semaphore interrupt
471 SEM_INT13 Semaphore interrupt
472 SEM_ERR12 Semaphore error interrupt
473 SEM_ERR13 Semaphore error interrupt
(1) 66AK2H12/14 only.

Table 8-25 CIC1 Event Inputs — C66x CorePac Secondary Interrupts

EVENT NO. EVENT NAME DESCRIPTION
0 EDMACC_1_ERRINT EDMA3CC1 error interrupt
1 EDMACC_1_MPINT EDMA3CC1 memory protection interrupt
2 EDMACC_1_TC_0_ERRINT EDMA3CC1 TPTC0 error interrupt
3 EDMACC_1_TC_1_ERRINT EDMA3CC1 TPTC1 error interrupt
4 EDMACC_1_TC_2_ERRINT EDMA3CC1 TPTC2 error interrupt
5 EDMACC_1_TC_3_ERRINT EDMA3CC1 TPTC3 error interrupt
6 EDMACC_1_GINT EDMA3CC1 GINT
7 Reserved Reserved
8 EDMACC_1_TC_0_INT EDMA3CC1 individual completion interrupt
9 EDMACC_1_TC_1_INT EDMA3CC1 individual completion interrupt
10 EDMACC_1_TC_2_INT EDMA3CC1 individual completion interrupt
11 EDMACC_1_TC_3_INT EDMA3CC1 individual completion interrupt
12 EDMACC_1_TC_4_INT EDMA3CC1 individual completion interrupt
13 EDMACC_1_TC_5_INT EDMA3CC1 individual completion interrupt
14 EDMACC_1_TC_6_INT EDMA3CC1 individual completion interrupt
15 EDMACC_1_TC_7_INT EDMA3CC1 individual completion interrupt
16 EDMACC_2_ERRINT EDMA3CC2 error interrupt
17 EDMACC_2_MPINT EDMA3CC2 memory protection interrupt
18 EDMACC_2_TC_0_ERRINT EDMA3CC2 TPTC0 error interrupt
19 EDMACC_2_TC_1_ERRINT EDMA3CC2 TPTC1 error interrupt
20 EDMACC_2_TC_2_ERRINT EDMA3CC2 TPTC2 error interrupt
21 EDMACC_2_TC_3_ERRINT EDMA3CC2 TPTC3 error interrupt
22 EDMACC_2_GINT EDMA3CC2 GINT
23 Reserved Reserved
24 EDMACC_2_TC_0_INT EDMA3CC2 individual completion interrupt
25 EDMACC_2_TC_1_INT EDMA3CC2 individual completion interrupt
26 EDMACC_2_TC_2_INT EDMA3CC2 individual completion interrupt
27 EDMACC_2_TC_3_INT EDMA3CC2 individual completion interrupt
28 EDMACC_2_TC_4_INT EDMA3CC2 individual completion interrupt
29 EDMACC_2_TC_5_INT EDMA3CC2 individual completion interrupt
30 EDMACC_2_TC_6_INT EDMA3CC2 individual completion interrupt
31 EDMACC_2_TC_7_INT EDMA3CC2 individual completion interrupt
32 EDMACC_0_ERRINT EDMA3CC0 error interrupt
33 EDMACC_0_MPINT EDMA3CC0 memory protection interrupt
34 EDMACC_0_TC_0_ERRINT EDMA3CC0 TPTC0 error interrupt
35 EDMACC_0_TC_1_ERRINT EDMA3CC0 TPTC1 error interrupt
36 EDMACC_0_GINT EDMA3CC0 GINT
37 Reserved Reserved
38 EDMACC_0_TC_0_INT EDMA3CC0 individual completion interrupt
39 EDMACC_0_TC_1_INT EDMA3CC0 individual completion interrupt
40 EDMACC_0_TC_2_INT EDMA3CC0 individual completion interrupt
41 EDMACC_0_TC_3_INT EDMA3CC0 individual completion interrupt
42 EDMACC_0_TC_4_INT EDMA3CC0 individual completion interrupt
43 EDMACC_0_TC_5_INT EDMA3CC0 individual completion interrupt
44 EDMACC_0_TC_6_INT EDMA3CC0 individual completion interrupt
45 EDMACC_0_TC_7_INT EDMA3CC0 individual completion interrupt
46 Reserved Reserved
47 QMSS_QUE_PEND_658 Navigator transmit queue pending event for indicated queue
48 PCIE_INT12 PCIE interrupt
49 PCIE_INT13 PCIE interrupt
50 PCIE_INT0 PCIE interrupt
51 PCIE_INT1 PCIE interrupt
52 PCIE_INT2 PCIE interrupt
53 PCIE_INT3 PCIE interrupt
54 SPI_0_INT0 SPI0 interrupt
55 SPI_0_INT1 SPI0 interrupt
56 SPI_0_XEVT SPI0 transmit event
57 SPI_0_REVT SPI0 receive event
58 I2C_0_INT I2C0 interrupt
59 I2C_0_REVT I2C0 receive event
60 I2C_0_XEVT I2C0 transmit event
61 Reserved Reserved
62 Reserved Reserved
63 DBGTBR_DMAINT Debug trace buffer (TBR) DMA event
64 MPU_12_INT MPU12 interrupt
65 DBGTBR_ACQCOMP Debug trace buffer (TBR) acquisition has been completed
66 MPU_13_INT MPU13 interrupt
67 MPU_14_INT MPU14 interrupt
68 NETCP_MDIO_LINK_INT0 Packet Accelerator 0 subsystem MDIO interrupt
69 NETCP_MDIO_LINK_INT1 Packet Accelerator 0 subsystem MDIO interrupt
70 NETCP_MDIO_USER_INT0 Packet Accelerator 0 subsystem MDIO interrupt
71 NETCP_MDIO_USER_INT1 Packet Accelerator 0 subsystem MDIO interrupt
72 NETCP_MISC_INT Packet Accelerator 0 subsystem misc interrupt
73 TRACER_CORE_0_INT Tracer sliding time window interrupt for DSP0 L2
74 TRACER_CORE_1_INT Tracer sliding time window interrupt for DSP1 L2
75 TRACER_CORE_2_INT Tracer sliding time window interrupt for DSP2 L2
76 TRACER_CORE_3_INT Tracer sliding time window interrupt for DSP3 L2
77 TRACER_DDR_INT Tracer sliding time window interrupt for MSMC-DDR3A
78 TRACER_MSMC_0_INT Tracer sliding time window interrupt for MSMC SRAM bank0
79 TRACER_MSMC_1_INT Tracer sliding time window interrupt for MSMC SRAM bank1
80 TRACER_MSMC_2_INT Tracer sliding time window interrupt for MSMC SRAM bank2
81 TRACER_MSMC_3_INT Tracer sliding time window interrupt for MSMC SRAM bank3
82 TRACER_CFG_INT Tracer sliding time window interrupt for CFG0 TeraNet
83 TRACER_QMSS_QM_CFG1_INT Tracer sliding time window interrupt for Navigator CFG1 slave port
84 TRACER_QMSS_DMA_INT Tracer sliding time window interrupt for Navigator DMA internal bus slave port
85 TRACER_SEM_INT Tracer sliding time window interrupt for Semaphore
86 PSC_ALLINT Power & Sleep Controller interrupt
87 MSMC_SCRUB_CERROR Correctable (1-bit) soft error detected during scrub cycle
88 BOOTCFG_INT Chip-level MMR Error Register
89 SR_0_PO_VCON_SMPSERR_INT SmartReflex SMPS error interrupt
90 MPU_0_INT MPU0 addressing violation interrupt and protection violation interrupt.
91 QMSS_QUE_PEND_659 Navigator transmit queue pending event for indicated queue
92 MPU_1_INT MPU1 addressing violation interrupt and protection violation interrupt.
93 QMSS_QUE_PEND_660 Navigator transmit queue pending event for indicated queue
94 MPU_2_INT MPU2 addressing violation interrupt and protection violation interrupt.
95 QMSS_QUE_PEND_661 Navigator transmit queue pending event for indicated queue
96 MPU_3_INT MPU3 addressing violation interrupt and protection violation interrupt.
97 QMSS_QUE_PEND_662 Navigator transmit queue pending event for indicated queue
98 MSMC_DEDC_CERROR Correctable (1-bit) soft error detected on SRAM read
99 MSMC_DEDC_NC_ERROR Noncorrectable (2-bit) soft error detected on SRAM read
100 MSMC_SCRUB_NC_ERROR Noncorrectable (2-bit) soft error detected during scrub cycle
101 Reserved Reserved
102 MSMC_MPF_ERROR8 Memory protection fault indicators for system master PrivID = 8
103 MSMC_MPF_ERROR9 Memory protection fault indicators for system master PrivID = 9
104 MSMC_MPF_ERROR10 Memory protection fault indicators for system master PrivID = 10
105 MSMC_MPF_ERROR11 Memory protection fault indicators for system master PrivID = 11
106 MSMC_MPF_ERROR12 Memory protection fault indicators for system master PrivID = 12
107 MSMC_MPF_ERROR13 Memory protection fault indicators for system master PrivID = 13
108 MSMC_MPF_ERROR14 Memory protection fault indicators for system master PrivID = 14
109 MSMC_MPF_ERROR15 Memory protection fault indicators for system master PrivID = 15
110 DDR3_0_ERR DDR3A_EMIF Error interrupt
111 HYPERLINK_0_INT HyperLink 0 interrupt
112 SRIO_INTDST0 SRIO interrupt
113 SRIO_INTDST1 SRIO interrupt
114 SRIO_INTDST2 SRIO interrupt
115 SRIO_INTDST3 SRIO interrupt
116 SRIO_INTDST4 SRIO interrupt
117 SRIO_INTDST5 SRIO interrupt
118 SRIO_INTDST6 SRIO interrupt
119 SRIO_INTDST7 SRIO interrupt
120 SRIO_INTDST8 SRIO interrupt
121 SRIO_INTDST9 SRIO interrupt
122 SRIO_INTDST10 SRIO interrupt
123 SRIO_INTDST11 SRIO interrupt
124 SRIO_INTDST12 SRIO interrupt
125 SRIO_INTDST13 SRIO interrupt
126 SRIO_INTDST14 SRIO interrupt
127 SRIO_INTDST15 SRIO interrupt
128 AEMIF_EASYNCERR Asynchronous EMIF16 error interrupt
129 TRACER_CORE_4_INT Tracer sliding time window interrupt for DSP4 L2(1)
130 TRACER_CORE_5_INT Tracer sliding time window interrupt for DSP5 L2(1)
131 TRACER_CORE_6_INT Tracer sliding time window interrupt for DSP6 L2(1)
132 TRACER_CORE_7_INT Tracer sliding time window interrupt for DSP7 L2(1)
133 QMSS_INTD_1_PKTDMA_0 Navigator interrupt for Packet DMA starvation
134 QMSS_INTD_1_PKTDMA_1 Navigator interrupt for Packet DMA starvation
135 SRIO_INT_PKTDMA_0 IPC interrupt generation
136 NETCP_PKTDMA_INT0 Packet Accelerator0 Packet DMA starvation interrupt
137 SR_0_SMARTREFLEX_INTREQ0 SmartReflex controller interrupt
138 SR_0_SMARTREFLEX_INTREQ1 SmartReflex controller interrupt
139 SR_0_SMARTREFLEX_INTREQ2 SmartReflex controller interrupt
140 SR_0_SMARTREFLEX_INTREQ3 SmartReflex controller interrupt
141 SR_0_VPNOSMPSACK SmartReflex VPVOLTUPDATE has been asserted but SMPS has not been responded to in a defined time interval
142 SR_0_VPEQVALUE SmartReflex SRSINTERUPT is asserted, but the new voltage is not different from the current SMPS voltage
143 SR_0_VPMAXVDD SmartReflex. The new voltage required is equal to or greater than MaxVdd
144 SR_0_VPMINVDD SmartReflex. The new voltage required is equal to or less than MinVdd
145 SR_0_VPINIDLE SmartReflex indicating that the FSM of voltage processor is in idle
146 SR_0_VPOPPCHANGEDONE SmartReflex indicating that the average frequency error is within the desired limit
147 Reserved Reserved
148 UART_0_UARTINT UART0 interrupt
149 UART_0_URXEVT UART0 receive event
150 UART_0_UTXEVT UART0 transmit event
151 QMSS_QUE_PEND_663 Navigator transmit queue pending event for indicated queue
152 QMSS_QUE_PEND_664 Navigator transmit queue pending event for indicated queue
153 QMSS_QUE_PEND_665 Navigator transmit queue pending event for indicated queue
154 QMSS_QUE_PEND_666 Navigator transmit queue pending event for indicated queue
155 QMSS_QUE_PEND_667 Navigator transmit queue pending event for indicated queue
156 QMSS_QUE_PEND_668 Navigator transmit queue pending event for indicated queue
157 QMSS_QUE_PEND_669 Navigator transmit queue pending event for indicated queue
158 QMSS_QUE_PEND_670 Navigator transmit queue pending event for indicated queue
159 QMSS_QUE_PEND_671 Navigator transmit queue pending event for indicated queue
160 SR_0_VPSMPSACK SmartReflex VPVOLTUPDATE asserted and SMPS has acknowledged in a defined time interval
161 ARM_TBR_DMA ARM trace buffer (TBR) DMA event
162 ARM_TBR_ACQ ARM trace buffer (TBR) Acquisition has been completed
163 ARM_NINTERRIRQ ARM internal memory ECC error interrupt request
164 ARM_NAXIERRIRQ ARM bus error interrupt request
165 SR_0_SR_TEMPSENSOR SmartReflex temperature threshold crossing interrupt
166 SR_0_SR_TIMERINT SmartReflex internal timer expiration interrupt
167 Reserved Reserved
168 Reserved Reserved
169 Reserved Reserved
170 Reserved Reserved
171 Reserved Reserved
172 Reserved Reserved
173 Reserved Reserved
174 Reserved Reserved
175 TIMER_7_INTL Timer interrupt low(1)
176 TIMER_7_INTH Timer interrupt high(1)
177 TIMER_6_INTL Timer interrupt low(1)
178 TIMER_6_INTH Timer interrupt high(1)
179 TIMER_5_INTL Timer interrupt low(1)
180 TIMER_5_INTH Timer interrupt high(1)
181 TIMER_4_INTL Timer interrupt low(1)
182 TIMER_4_INTH Timer interrupt high(1)
183 TIMER_3_INTL Timer interrupt low
184 TIMER_3_INTH Timer interrupt high
185 TIMER_2_INTL Timer interrupt low
186 TIMER_2_INTH Timer interrupt high
187 TIMER_1_INTL Timer interrupt low
188 TIMER_1_INTH Timer interrupt high
189 TIMER_0_INTL Timer interrupt low
190 TIMER_0_INTH Timer interrupt high
191 Reserved Reserved
192 Reserved Reserved
193 Reserved Reserved
194 Reserved Reserved
195 Reserved Reserved
196 Reserved Reserved
197 Reserved Reserved
198 Reserved Reserved
199 Reserved Reserved
200 Reserved Reserved
201 Reserved Reserved
202 Reserved Reserved
203 Reserved Reserved
204 Reserved Reserved
205 Reserved Reserved
206 Reserved Reserved
207 EDMACC_4_ERRINT EDMA3CC4 error interrupt
208 EDMACC_4_MPINT EDMA3CC4 memory protection interrupt
209 EDMACC_4_TC_0_ERRINT EDMA3CC4 TPTC0 error interrupt
210 EDMACC_4_TC_1_ERRINT EDMA3CC4 TPTC1 error interrupt
211 EDMACC_4_GINT EDMA3CC4 GINT
212 EDMACC_4_TC_0_INT EDMA3CC4 individual completion interrupt
213 EDMACC_4_TC_1_INT EDMA3CC4 individual completion interrupt
214 EDMACC_4_TC_2_INT EDMA3CC4 individual completion interrupt
215 EDMACC_4_TC_3_INT EDMA3CC4 individual completion interrupt
216 EDMACC_4_TC_4_INT EDMA3CC4 individual completion interrupt
217 EDMACC_4_TC_5_INT EDMA3CC4 individual completion interrupt
218 EDMACC_4_TC_6_INT EDMA3CC4 individual completion interrupt
219 EDMACC_4_TC_7_INT EDMA3CC4 individual completion interrupt
220 EDMACC_3_ERRINT EDMA3CC3 error interrupt
221 EDMACC_3_MPINT EDMA3CC3 memory protection interrupt
222 EDMACC_3_TC_0_ERRINT EDMA3CC3 TPTC0 error interrupt
223 EDMACC_3_TC_1_ERRINT EDMA3CC3 TPTC1 error interrupt
224 EDMACC_3_GINT EDMA3CC3 GINT
225 EDMACC_3_TC_0_INT EDMA3CC3 individual completion interrupt
226 EDMACC_3_TC_1_INT EDMA3CC3 individual completion interrupt
227 EDMACC_3_TC_2_INT EDMA3CC3 individual completion interrupt
228 EDMACC_3_TC_3_INT EDMA3CC3 individual completion interrupt
229 EDMACC_3_TC_4_INT EDMA3CC3 individual completion interrupt
230 EDMACC_3_TC_5_INT EDMA3CC3 individual completion interrupt
231 EDMACC_3_TC_6_INT EDMA3CC3 individual completion interrupt
232 EDMACC_3_TC_7_INT EDMA3CC3 individual completion interrupt
233 UART_1_UARTINT UART1 interrupt
234 UART_1_URXEVT UART1 receive event
235 UART_1_UTXEVT UART1 transmit event
236 I2C_1_INT I2C1 interrupt
237 I2C_1_REVT I2C1 receive event
238 I2C_1_XEVT I2C1 transmit event
239 SPI_1_INT0 SPI1 interrupt0
240 SPI_1_INT1 SPI1 interrupt1
241 SPI_1_XEVT SPI1 transmit event
242 SPI_1_REVT SPI1 receive event
243 MPU_5_INT MPU5 addressing violation interrupt and protection violation interrupt
244 MPU_8_INT MPU8 addressing violation interrupt and protection violation interrupt
245 MPU_9_INT MPU9 addressing violation interrupt and protection violation interrupt
246 MPU_11_INT MPU11 addressing violation interrupt and protection violation interrupt
247 MPU_4_INT MPU4 addressing violation interrupt and protection violation interrupt
248 MPU_6_INT MPU6 addressing violation interrupt and protection violation interrupt
249 MPU_7_INT MPU7 addressing violation interrupt and protection violation interrupt
250 MPU_10_INT MPU10 addressing violation interrupt and protection violation interrupt
251 SPI_2_INT0 SPI2 interrupt0
252 SPI_2_INT1 SPI2 interrupt1
253 SPI_2_XEVT SPI2 transmit event
254 SPI_2_REVT SPI2 receive event
255 I2C_2_INT I2C2 interrupt
256 I2C_2_REVT I2C2 receive event
257 I2C_2_XEVT I2C2 transmit event
258 10GbE_LINK_INT0 10 Gigabit Ethernet subsystem MDIO interrupt (66AK2H14 only)
259 10GbE_LINK_INT1 10 Gigabit Ethernet subsystem MDIO interrupt (66AK2H14 only)
260 10GbE_USER_INT0 10 Gigabit Ethernet subsystem MDIO interrupt (66AK2H14 only)
261 10GbE_USER_INT1 10 Gigabit Ethernet subsystem MDIO interrupt (66AK2H14 only)
262 10GbE_MISC_INT 10 Gigabit Ethernet subsystem MDIO interrupt (66AK2H14 only)
263 10GbE_INT_PKTDMA_0 10 Gigabit Ethernet Packet DMA starvation interrupt (66AK2H14 only)
264 Reserved Reserved
265 Reserved Reserved
266 Reserved Reserved
267 Reserved Reserved
268 Reserved Reserved
269 Reserved Reserved
270 Reserved Reserved
271 Reserved Reserved
272 Reserved Reserved
273 Reserved Reserved
274 Reserved Reserved
275 Reserved Reserved
276 Reserved Reserved
277 Reserved Reserved
278 Reserved Reserved
279 Reserved Reserved
280 Reserved Reserved
281 Reserved Reserved
282 Reserved Reserved
283 Reserved Reserved
284 Reserved Reserved
285 Reserved Reserved
286 Reserved Reserved
287 Reserved Reserved
288 Reserved Reserved
289 Reserved Reserved
290 Reserved Reserved
291 Reserved Reserved
292 QMSS_QUE_PEND_652 Navigator transmit queue pending event for indicated queue
293 QMSS_QUE_PEND_653 Navigator transmit queue pending event for indicated queue
294 QMSS_QUE_PEND_654 Navigator transmit queue pending event for indicated queue
295 QMSS_QUE_PEND_655 Navigator transmit queue pending event for indicated queue
296 QMSS_QUE_PEND_656 Navigator transmit queue pending event for indicated queue
297 QMSS_QUE_PEND_657 Navigator transmit queue pending event for indicated queue
298 QMSS_QUE_PEND_8844 Navigator transmit queue pending event for indicated queue
299 QMSS_QUE_PEND_8845 Navigator transmit queue pending event for indicated queue
300 QMSS_QUE_PEND_8846 Navigator transmit queue pending event for indicated queue
301 QMSS_QUE_PEND_8847 Navigator transmit queue pending event for indicated queue
302 QMSS_QUE_PEND_8848 Navigator transmit queue pending event for indicated queue
303 QMSS_QUE_PEND_8849 Navigator transmit queue pending event for indicated queue
304 QMSS_QUE_PEND_8850 Navigator transmit queue pending event for indicated queue
305 QMSS_QUE_PEND_8851 Navigator transmit queue pending event for indicated queue
306 QMSS_QUE_PEND_8852 Navigator transmit queue pending event for indicated queue
307 QMSS_QUE_PEND_8853 Navigator transmit queue pending event for indicated queue
308 QMSS_QUE_PEND_8854 Navigator transmit queue pending event for indicated queue
309 QMSS_QUE_PEND_8855 Navigator transmit queue pending event for indicated queue
310 QMSS_QUE_PEND_8856 Navigator transmit queue pending event for indicated queue
311 QMSS_QUE_PEND_8857 Navigator transmit queue pending event for indicated queue
312 QMSS_QUE_PEND_8858 Navigator transmit queue pending event for indicated queue
313 QMSS_QUE_PEND_8859 Navigator transmit queue pending event for indicated queue
314 QMSS_QUE_PEND_8860 Navigator transmit queue pending event for indicated queue
315 QMSS_QUE_PEND_8861 Navigator transmit queue pending event for indicated queue
316 QMSS_QUE_PEND_8862 Navigator transmit queue pending event for indicated queue
317 QMSS_QUE_PEND_8863 Navigator transmit queue pending event for indicated queue
318 QMSS_INTD_2_PKTDMA_0 Navigator ECC error interrupt
319 QMSS_INTD_2_PKTDMA_1 Navigator ECC error interrupt
320 QMSS_INTD_1_LOW_0 Navigator interrupt low
321 QMSS_INTD_1_LOW_1 Navigator interrupt low
322 QMSS_INTD_1_LOW_2 Navigator interrupt low
323 QMSS_INTD_1_LOW_3 Navigator interrupt low
324 QMSS_INTD_1_LOW_4 Navigator interrupt low
325 QMSS_INTD_1_LOW_5 Navigator interrupt low
326 QMSS_INTD_1_LOW_6 Navigator interrupt low
327 QMSS_INTD_1_LOW_7 Navigator interrupt low
328 QMSS_INTD_1_LOW_8 Navigator interrupt low
329 QMSS_INTD_1_LOW_9 Navigator interrupt low
330 QMSS_INTD_1_LOW_10 Navigator interrupt low
331 QMSS_INTD_1_LOW_11 Navigator interrupt low
332 QMSS_INTD_1_LOW_12 Navigator interrupt low
333 QMSS_INTD_1_LOW_13 Navigator interrupt low
334 QMSS_INTD_1_LOW_14 Navigator interrupt low
335 QMSS_INTD_1_LOW_15 Navigator interrupt low
336 QMSS_INTD_2_LOW_0 Navigator second interrupt low
337 QMSS_INTD_2_LOW_1 Navigator second interrupt low
338 QMSS_INTD_2_LOW_2 Navigator second interrupt low
339 QMSS_INTD_2_LOW_3 Navigator second interrupt low
340 QMSS_INTD_2_LOW_4 Navigator second interrupt low
341 QMSS_INTD_2_LOW_5 Navigator second interrupt low
342 QMSS_INTD_2_LOW_6 Navigator second interrupt low
343 QMSS_INTD_2_LOW_7 Navigator second interrupt low
344 QMSS_INTD_2_LOW_8 Navigator second interrupt low
345 QMSS_INTD_2_LOW_9 Navigator second interrupt low
346 QMSS_INTD_2_LOW_10 Navigator second interrupt low
347 QMSS_INTD_2_LOW_11 Navigator second interrupt low
348 QMSS_INTD_2_LOW_12 Navigator second interrupt low
349 QMSS_INTD_2_LOW_13 Navigator second interrupt low
350 QMSS_INTD_2_LOW_14 Navigator second interrupt low
351 QMSS_INTD_2_LOW_15 Navigator second interrupt low
352 TRACER_EDMACC_0 Tracer sliding time window interrupt for EDMA3CC0
353 TRACER_EDMACC_123_INT Tracer sliding time window interrupt for EDMA3CC1, EDMA3CC2 and EDMA3CC3
354 TRACER_CIC_INT Tracer sliding time window interrupt for interrupt controllers (CIC)
355 TRACER_MSMC_4_INT Tracer sliding time window interrupt for MSMC SRAM bank4
356 TRACER_MSMC_5_INT Tracer sliding time window interrupt for MSMC SRAM bank5
357 TRACER_MSMC_6_INT Tracer sliding time window interrupt for MSMC SRAM bank6
358 TRACER_MSMC_7_INT Tracer sliding time window interrupt for MSMC SRAM bank7
359 TRACER_SPI_ROM_EMIF_INT Tracer sliding time window interrupt for SPI/ROM/EMIF16 modules
360 TRACER_QMSS_QM_CFG2_INT Tracer sliding time window interrupt for QM2
361 Reserved Reserved
362 Reserved Reserved
363 TRACER_DDR_1_INT Tracer sliding time window interrupt for DDR3B
364 Reserved Reserved
365 HYPERLINK_1_INT HyperLink 1 interrupt
366 Reserved Reserved
367 Reserved Reserved
368 Reserved Reserved
369 Reserved Reserved
370 Reserved Reserved
371 Reserved Reserved
372 Reserved Reserved
373 Reserved Reserved
374 Reserved Reserved
375 Reserved Reserved
376 Reserved Reserved
377 Reserved Reserved
378 Reserved Reserved
379 Reserved Reserved
380 Reserved Reserved
381 Reserved Reserved
382 Reserved Reserved
383 Reserved Reserved
384 Reserved Reserved
385 Reserved Reserved
386 Reserved Reserved
387 Reserved Reserved
388 Reserved Reserved
389 Reserved Reserved
390 Reserved Reserved
391 Reserved Reserved
392 Reserved Reserved
393 Reserved Reserved
394 Reserved Reserved
395 Reserved Reserved
396 Reserved Reserved
397 Reserved Reserved
398 Reserved Reserved
399 Reserved Reserved
400 Reserved Reserved
401 Reserved Reserved
402 Reserved Reserved
403 Reserved Reserved
404 Reserved Reserved
405 Reserved Reserved
406 Reserved Reserved
407 Reserved Reserved
408 Reserved Reserved
409 Reserved Reserved
410 Reserved Reserved
411 Reserved Reserved
412 Reserved Reserved
413 Reserved Reserved
414 Reserved Reserved
415 Reserved Reserved
416 Reserved Reserved
417 Reserved Reserved
418 Reserved Reserved
419 Reserved Reserved
420 Reserved Reserved
421 Reserved Reserved
422 USB_INT00 USB interrupt
423 USB_INT04 USB interrupt
424 USB_INT05 USB interrupt
425 USB_INT06 USB interrupt
426 USB_INT07 USB interrupt
427 USB_INT08 USB interrupt
428 USB_INT09 USB interrupt
429 USB_INT10 USB interrupt
430 USB_INT11 USB interrupt
431 USB_MISCINT USB miscellaneous interrupt
432 USB_OABSINT USB OABS interrupt
433 TIMER_12_INTL Timer interrupt low
434 TIMER_12_INTH Timer interrupt high
435 TIMER_13_INTL Timer interrupt low
436 TIMER_13_INTH Timer interrupt high
437 TIMER_14_INTL Timer interrupt low
438 TIMER_14_INTH Timer interrupt high
439 TIMER_15_INTL Timer interrupt low
440 TIMER_15_INTH Timer interrupt high
441 TIMER_16_INTL Timer interrupt low
442 TIMER_17_INTL Timer interrupt high
443 TIMER_18_INTL Timer interrupt low(1)
444 TIMER_19_INTL Timer interrupt high(1)
445 DDR3_1_ERR DDR3B_EMIF error interrupt
446 GPIO_INT16 GPIO interrupt
447 GPIO_INT17 GPIO interrupt
448 GPIO_INT18 GPIO interrupt
449 GPIO_INT19 GPIO interrupt
450 GPIO_INT20 GPIO interrupt
451 GPIO_INT21 GPIO interrupt
452 GPIO_INT22 GPIO interrupt
453 GPIO_INT23 GPIO interrupt
454 GPIO_INT24 GPIO interrupt
455 GPIO_INT25 GPIO interrupt
456 GPIO_INT26 GPIO interrupt
457 GPIO_INT27 GPIO interrupt
458 GPIO_INT28 GPIO interrupt
459 GPIO_INT29 GPIO interrupt
460 GPIO_INT30 GPIO interrupt
461 GPIO_INT31 GPIO interrupt
462 SRIO_INTDST20 SRIOI interrupt
463 SRIO_INTDST21 SRIOI interrupt
464 SRIO_INTDST22 SRIOI interrupt
465 SRIO_INTDST23 SRIOI interrupt
466 PCIE_INT8 PCIE MSI interrupt
467 PCIE_INT9 PCIE MSI interrupt
468 PCIE_INT10 PCIE MSI interrupt
469 PCIE_INT11 PCIE MSI interrupt
470 SEM_INT12 Semaphore interrupt
471 SEM_INT13 Semaphore interrupt
472 SEM_ERR12 Semaphore error interrupt
473 SEM_ERR13 Semaphore error interrupt
474 Reserved Reserved
(1) 66AK2H12/14 only.

Table 8-26 CIC2 Event Inputs (Secondary Events for EDMA3CC0 and Hyperlinks)

EVENT NO. EVENT NAME DESCRIPTION
0 GPIO_INT8 GPIO interrupt
1 GPIO_INT9 GPIO interrupt
2 GPIO_INT10 GPIO interrupt
3 GPIO_INT11 GPIO interrupt
4 GPIO_INT12 GPIO interrupt
5 GPIO_INT13 GPIO interrupt
6 GPIO_INT14 GPIO interrupt
7 GPIO_INT15 GPIO interrupt
8 DBGTBR_DMAINT Debug trace buffer (TBR) DMA event
9 Reserved Reserved
10 Reserved Reserved
11 TETB_FULLINT0 TETB0 is full
12 TETB_HFULLINT0 TETB0 is half full
13 TETB_ACQINT0 TETB0 acquisition has been completed
14 TETB_FULLINT1 TETB1 is full
15 TETB_HFULLINT1 TETB1 is half full
16 TETB_ACQINT1 TETB1 acquisition has been completed
17 TETB_FULLINT2 TETB2 is full
18 TETB_HFULLINT2 TETB2 is half full
19 TETB_ACQINT2 TETB2 acquisition has been completed
20 TETB_FULLINT3 TETB3 is full
21 TETB_HFULLINT3 TETB3 is half full
22 TETB_ACQINT3 TETB3 acquisition has been completed
23 Reserved Reserved
24 QMSS_INTD_1_HIGH_16 Navigator hi interrupt
25 QMSS_INTD_1_HIGH_17 Navigator hi interrupt
26 QMSS_INTD_1_HIGH_18 Navigator hi interrupt
27 QMSS_INTD_1_HIGH_19 Navigator hi interrupt
28 QMSS_INTD_1_HIGH_20 Navigator hi interrupt
29 QMSS_INTD_1_HIGH_21 Navigator hi interrupt
30 QMSS_INTD_1_HIGH_22 Navigator hi interrupt
31 QMSS_INTD_1_HIGH_23 Navigator hi interrupt
32 QMSS_INTD_1_HIGH_24 Navigator hi interrupt
33 QMSS_INTD_1_HIGH_25 Navigator hi interrupt
34 QMSS_INTD_1_HIGH_26 Navigator hi interrupt
35 QMSS_INTD_1_HIGH_27 Navigator hi interrupt
36 QMSS_INTD_1_HIGH_28 Navigator hi interrupt
37 QMSS_INTD_1_HIGH_29 Navigator hi interrupt
38 QMSS_INTD_1_HIGH_30 Navigator hi interrupt
39 QMSS_INTD_1_HIGH_31 Navigator hi interrupt
40 NETCP_MDIO_LINK_INT0 Packet Accelerator 0 subsystem MDIO interrupt
41 NETCP_MDIO_LINK_INT1 Packet Accelerator 0 subsystem MDIO interrupt
42 NETCP_MDIO_USER_INT0 Packet Accelerator 0 subsystem MDIO interrupt
43 NETCP_MDIO_USER_INT1 Packet Accelerator 0 subsystem MDIO interrupt
44 NETCP_MISC_INT Packet Accelerator 0 subsystem MDIO interrupt
45 TRACER_CORE_0_INT Tracer sliding time window interrupt for DSP0 L2
46 TRACER_CORE_1_INT Tracer sliding time window interrupt for DSP1 L2
47 TRACER_CORE_2_INT Tracer sliding time window interrupt for DSP2 L2
48 TRACER_CORE_3_INT Tracer sliding time window interrupt for DSP3 L2
49 TRACER_DDR_INT Tracer sliding time window interrupt for MSMC-DDR3A
50 TRACER_MSMC_0_INT Tracer sliding time window interrupt for MSMC SRAM bank0
51 TRACER_MSMC_1_INT Tracer sliding time window interrupt for MSMC SRAM bank1
52 TRACER_MSMC_2_INT Tracer sliding time window interrupt for MSMC SRAM bank2
53 TRACER_MSMC_3_INT Tracer sliding time window interrupt for MSMC SRAM bank3
54 TRACER_CFG_INT Tracer sliding time window interrupt for TeraNet CFG
55 TRACER_QMSS_QM_CFG1_INT Tracer sliding time window interrupt for Navigator CFG1 slave port
56 TRACER_QMSS_DMA_INT Tracer sliding time window interrupt for Navigator DMA internal bus slave port
57 TRACER_SEM_INT Tracer sliding time window interrupt for Semaphore interrupt
58 SEM_ERR0 Semaphore error interrupt
59 SEM_ERR1 Semaphore error interrupt
60 SEM_ERR2 Semaphore error interrupt
61 SEM_ERR3 Semaphore error interrupt
62 BOOTCFG_INT BOOTCFG error interrupt
63 NETCP_PKTDMA_INT0 Packet Accelerator0 Packet DMA starvation interrupt
64 MPU_0_INT MPU0 interrupt
65 MSMC_SCRUB_CERROR MSMC error interrupt
66 MPU_1_INT MPU1 interrupt
67 SRIO_INT_PKTDMA_0 Packet Accelerator0 Packet DMA interrupt
68 MPU_2_INT MPU2 interrupt
69 QMSS_INTD_1_PKTDMA_0 Navigator Packet DMA interrupt
70 MPU_3_INT MPU3 interrupt
71 QMSS_INTD_1_PKTDMA_1 Navigator Packet DMA interrupt
72 MSMC_DEDC_CERROR MSMC error interrupt
73 MSMC_DEDC_NC_ERROR MSMC error interrupt
74 MSMC_SCRUB_NC_ERROR MSMC error interrupt
75 Reserved Reserved
76 MSMC_MPF_ERROR0 Memory protection fault indicators for system master PrivID = 0
77 MSMC_MPF_ERROR1 Memory protection fault indicators for system master PrivID = 1
78 MSMC_MPF_ERROR2 Memory protection fault indicators for system master PrivID = 2
79 MSMC_MPF_ERROR3 Memory protection fault indicators for system master PrivID = 3
80 MSMC_MPF_ERROR4 Memory protection fault indicators for system master PrivID = 4
81 MSMC_MPF_ERROR5 Memory protection fault indicators for system master PrivID = 5
82 MSMC_MPF_ERROR6 Memory protection fault indicators for system master PrivID = 6
83 MSMC_MPF_ERROR7 Memory protection fault indicators for system master PrivID = 7
84 MSMC_MPF_ERROR8 Memory protection fault indicators for system master PrivID = 8
85 MSMC_MPF_ERROR9 Memory protection fault indicators for system master PrivID = 9
86 MSMC_MPF_ERROR10 Memory protection fault indicators for system master PrivID = 10
87 MSMC_MPF_ERROR11 Memory protection fault indicators for system master PrivID = 11
88 MSMC_MPF_ERROR12 Memory protection fault indicators for system master PrivID = 12
89 MSMC_MPF_ERROR13 Memory protection fault indicators for system master PrivID = 13
90 MSMC_MPF_ERROR14 Memory protection fault indicators for system master PrivID = 14
91 MSMC_MPF_ERROR15 Memory protection fault indicators for system master PrivID = 15
92 Reserved Reserved
93 SRIO_INTDST0 SRIO interrupt
94 SRIO_INTDST1 SRIO interrupt
95 SRIO_INTDST2 SRIO interrupt
96 SRIO_INTDST3 SRIO interrupt
97 SRIO_INTDST4 SRIO interrupt
98 SRIO_INTDST5 SRIO interrupt
99 SRIO_INTDST6 SRIO interrupt
100 SRIO_INTDST7 SRIO interrupt
101 SRIO_INTDST8 SRIO interrupt
102 SRIO_INTDST9 SRIO interrupt
103 SRIO_INTDST10 SRIO interrupt
104 SRIO_INTDST11 SRIO interrupt
105 SRIO_INTDST12 SRIO interrupt
106 SRIO_INTDST13 SRIO interrupt
107 SRIO_INTDST14 SRIO interrupt
108 SRIO_INTDST15 SRIO interrupt
109 SRIO_INTDST16 SRIO interrupt
110 SRIO_INTDST17 SRIO interrupt
111 SRIO_INTDST18 SRIO interrupt
112 SRIO_INTDST19 SRIO interrupt
113 SRIO_INTDST20 SRIO interrupt
114 SRIO_INTDST21 SRIO interrupt
115 SRIO_INTDST22 SRIO interrupt
116 SRIO_INTDST23 SRIO interrupt
117 AEMIF_EASYNCERR Asynchronous EMIF16 error interrupt
118 TETB_FULLINT4 TETB4 is full
119 TETB_HFULLINT4 TETB4 is half full
120 TETB_ACQINT4 TETB4 acquisition has been completed
121 TETB_FULLINT5 TETB5 is full
122 TETB_HFULLINT5 TETB5 is half full
123 TETB_ACQINT5 TETB5 acquisition has been completed
124 TETB_FULLINT6 TETB6 is full
125 TETB_HFULLINT6 TETB6 is half full
126 TETB_ACQINT6 TETB6 acquisition has been completed
127 TETB_FULLINT7 TETB7 is full
128 TETB_HFULLINT7 TETB7 is half full
129 TETB_ACQINT7 TETB7 acquisition has been completed
130 TRACER_CORE_4_INT Tracer sliding time window interrupt for DSP4 L2
131 TRACER_CORE_5_INT Tracer sliding time window interrupt for DSP5 L2
132 TRACER_CORE_6_INT Tracer sliding time window interrupt for DSP6 L2
133 TRACER_CORE_7_INT Tracer sliding time window interrupt for DSP7 L2
134 SEM_ERR4 Semaphore error interrupt
135 SEM_ERR5 Semaphore error interrupt
136 SEM_ERR6 Semaphore error interrupt
137 SEM_ERR7 Semaphore error interrupt
138 QMSS_INTD_1_HIGH_0 Navigator hi interrupt
139 QMSS_INTD_1_HIGH_1 Navigator hi interrupt
140 QMSS_INTD_1_HIGH_2 Navigator hi interrupt
141 QMSS_INTD_1_HIGH_3 Navigator hi interrupt
142 QMSS_INTD_1_HIGH_4 Navigator hi interrupt
143 QMSS_INTD_1_HIGH_5 Navigator hi interrupt
144 QMSS_INTD_1_HIGH_6 Navigator hi interrupt
145 QMSS_INTD_1_HIGH_7 Navigator hi interrupt
146 QMSS_INTD_1_HIGH_8 Navigator hi interrupt
147 QMSS_INTD_1_HIGH_9 Navigator hi interrupt
148 QMSS_INTD_1_HIGH_10 Navigator hi interrupt
149 QMSS_INTD_1_HIGH_11 Navigator hi interrupt
150 QMSS_INTD_1_HIGH_12 Navigator hi interrupt
151 QMSS_INTD_1_HIGH_13 Navigator hi interrupt
152 QMSS_INTD_1_HIGH_14 Navigator hi interrupt
153 QMSS_INTD_1_HIGH_15 Navigator hi interrupt
154 QMSS_INTD_2_HIGH_0 Navigator second hi interrupt
155 QMSS_INTD_2_HIGH_1 Navigator second hi interrupt
156 QMSS_INTD_2_HIGH_2 Navigator second hi interrupt
157 QMSS_INTD_2_HIGH_3 Navigator second hi interrupt
158 QMSS_INTD_2_HIGH_4 Navigator second hi interrupt
159 QMSS_INTD_2_HIGH_5 Navigator second hi interrupt
160 QMSS_INTD_2_HIGH_6 Navigator second hi interrupt
161 QMSS_INTD_2_HIGH_7 Navigator second hi interrupt
162 QMSS_INTD_2_HIGH_8 Navigator second hi interrupt
163 QMSS_INTD_2_HIGH_9 Navigator second hi interrupt
164 QMSS_INTD_2_HIGH_10 Navigator second hi interrupt
165 QMSS_INTD_2_HIGH_11 Navigator second hi interrupt
166 QMSS_INTD_2_HIGH_12 Navigator second hi interrupt
167 QMSS_INTD_2_HIGH_13 Navigator second hi interrupt
168 QMSS_INTD_2_HIGH_14 Navigator second hi interrupt
169 QMSS_INTD_2_HIGH_15 Navigator second hi interrupt
170 QMSS_INTD_2_HIGH_16 Navigator second hi interrupt
171 QMSS_INTD_2_HIGH_17 Navigator second hi interrupt
172 QMSS_INTD_2_HIGH_18 Navigator second hi interrupt
173 QMSS_INTD_2_HIGH_19 Navigator second hi interrupt
174 QMSS_INTD_2_HIGH_20 Navigator second hi interrupt
175 QMSS_INTD_2_HIGH_21 Navigator second hi interrupt
176 QMSS_INTD_2_HIGH_22 Navigator second hi interrupt
177 QMSS_INTD_2_HIGH_23 Navigator second hi interrupt
178 QMSS_INTD_2_HIGH_24 Navigator second hi interrupt
179 QMSS_INTD_2_HIGH_25 Navigator second hi interrupt
180 QMSS_INTD_2_HIGH_26 Navigator second hi interrupt
181 QMSS_INTD_2_HIGH_27 Navigator second hi interrupt
182 QMSS_INTD_2_HIGH_28 Navigator second hi interrupt
183 QMSS_INTD_2_HIGH_29 Navigator second hi interrupt
184 QMSS_INTD_2_HIGH_30 Navigator second hi interrupt
185 QMSS_INTD_2_HIGH_31 Navigator second hi interrupt
186 MPU_12_INT MPU12 addressing violation interrupt and protection violation interrupt
187 MPU_13_INT MPU13 addressing violation interrupt and protection violation interrupt
188 MPU_14_INT MPU14 addressing violation interrupt and protection violation interrupt
189 Reserved Reserved
190 Reserved Reserved
191 Reserved Reserved
192 Reserved Reserved
193 Reserved Reserved
194 Reserved Reserved
195 Reserved Reserved
196 Reserved Reserved
197 Reserved Reserved
198 Reserved Reserved
199 TRACER_QMSS_QM_CFG2_INT Tracer sliding time window interrupt for Navigator CFG2 slave port
200 TRACER_EDMACC_0 Tracer sliding time window interrupt foR EDMA3CC0
201 TRACER_EDMACC_123_INT Tracer sliding time window interrupt for EDMA3CC1, EDMA3CC2 and EDMA3CC3
202 TRACER_CIC_INT Tracer sliding time window interrupt for interrupt controllers (CIC)
203 Reserved Reserved
204 MPU_5_INT MPU5 addressing violation interrupt and protection violation interrupt
205 Reserved Reserved
206 MPU_7_INT MPU7 addressing violation interrupt and protection violation interrupt
207 MPU_8_INT MPU8 addressing violation interrupt and protection violation interrupt
208 QMSS_INTD_2_PKTDMA_0 Navigator ECC error interrupt
209 QMSS_INTD_2_PKTDMA_1 Navigator ECC error interrupt
210 SR_0_VPSMPSACK SmartReflex VPVOLTUPDATE asserted and SMPS has acknowledged in a defined time interval
211 DDR3_0_ERR DDR3A error interrupt
212 HYPERLINK_0_INT HyperLink 0 interrupt
213 EDMACC_0_ERRINT EDMA3CC0 error interrupt
214 EDMACC_0_MPINT EDMA3CC0 memory protection interrupt
215 EDMACC_0_TC_0_ERRINT EDMA3CC0 TPTC0 error interrupt
216 EDMACC_0_TC_1_ERRINT EDMA3CC0 TPTC1 error interrupt
217 EDMACC_1_ERRINT EDMA3CC1 error interrupt
218 EDMACC_1_MPINT EDMA3CC1 memory protection interrupt
219 EDMACC_1_TC_0_ERRINT EDMA3CC1 TPTC0 error interrupt
220 EDMACC_1_TC_1_ERRINT EDMA3CC1 TPTC1 error interrupt
221 EDMACC_1_TC_2_ERRINT EDMA3CC1 TPTC2 error interrupt
222 EDMACC_1_TC_3_ERRINT EDMA3CC1 TPTC3 error interrupt
223 EDMACC_2_ERRINT EDMA3CC2 error interrupt
224 EDMACC_2_MPINT EDMA3CC2 memory protection interrupt
225 EDMACC_2_TC_0_ERRINT EDMA3CC2 TPTC0 error interrupt
226 EDMACC_2_TC_1_ERRINT EDMA3CC2 TPTC1 error interrupt
227 EDMACC_2_TC_2_ERRINT EDMA3CC2 TPTC2 error interrupt
228 EDMACC_2_TC_3_ERRINT EDMA3CC2 TPTC3 error interrupt
229 EDMACC_3_ERRINT EDMA3CC3 error interrupt
230 EDMACC_3_MPINT EDMA3CC3 memory protection interrupt
231 EDMACC_3_TC_0_ERRINT EDMA3CC3 TPTC0 error interrupt
232 EDMACC_3_TC_1_ERRINT EDMA3CC3 TPTC1 error interrupt
233 EDMACC_4_ERRINT EDMA3CC4 error interrupt
234 EDMACC_4_MPINT EDMA3CC4 memory protection interrupt
235 EDMACC_4_TC_0_ERRINT EDMA3CC4 TPTC0 error interrupt
236 EDMACC_4_TC_1_ERRINT EDMA3CC4 TPTC1 error interrupt
237 QMSS_QUE_PEND_652 Navigator transmit queue pending event for indicated queue
238 QMSS_QUE_PEND_653 Navigator transmit queue pending event for indicated queue
239 QMSS_QUE_PEND_654 Navigator transmit queue pending event for indicated queue
240 QMSS_QUE_PEND_655 Navigator transmit queue pending event for indicated queue
241 QMSS_QUE_PEND_656 Navigator transmit queue pending event for indicated queue
242 QMSS_QUE_PEND_657 Navigator transmit queue pending event for indicated queue
243 QMSS_QUE_PEND_658 Navigator transmit queue pending event for indicated queue
244 QMSS_QUE_PEND_659 Navigator transmit queue pending event for indicated queue
245 QMSS_QUE_PEND_660 Navigator transmit queue pending event for indicated queue
246 QMSS_QUE_PEND_661 Navigator transmit queue pending event for indicated queue
247 QMSS_QUE_PEND_662 Navigator transmit queue pending event for indicated queue
248 QMSS_QUE_PEND_663 Navigator transmit queue pending event for indicated queue
249 QMSS_QUE_PEND_664 Navigator transmit queue pending event for indicated queue
250 QMSS_QUE_PEND_665 Navigator transmit queue pending event for indicated queue
251 QMSS_QUE_PEND_666 Navigator transmit queue pending event for indicated queue
252 QMSS_QUE_PEND_667 Navigator transmit queue pending event for indicated queue
253 QMSS_QUE_PEND_668 Navigator transmit queue pending event for indicated queue
254 QMSS_QUE_PEND_669 Navigator transmit queue pending event for indicated queue
255 QMSS_QUE_PEND_670 Navigator transmit queue pending event for indicated queue
256 QMSS_QUE_PEND_671 Navigator transmit queue pending event for indicated queue
257 QMSS_QUE_PEND_8844 Navigator transmit queue pending event for indicated queue
258 QMSS_QUE_PEND_8845 Navigator transmit queue pending event for indicated queue
259 QMSS_QUE_PEND_8846 Navigator transmit queue pending event for indicated queue
260 QMSS_QUE_PEND_8847 Navigator transmit queue pending event for indicated queue
261 QMSS_QUE_PEND_8848 Navigator transmit queue pending event for indicated queue
262 QMSS_QUE_PEND_8849 Navigator transmit queue pending event for indicated queue
263 QMSS_QUE_PEND_8850 Navigator transmit queue pending event for indicated queue
264 QMSS_QUE_PEND_8851 Navigator transmit queue pending event for indicated queue
265 QMSS_QUE_PEND_8852 Navigator transmit queue pending event for indicated queue
266 QMSS_QUE_PEND_8853 Navigator transmit queue pending event for indicated queue
267 QMSS_QUE_PEND_8854 Navigator transmit queue pending event for indicated queue
268 QMSS_QUE_PEND_8855 Navigator transmit queue pending event for indicated queue
269 QMSS_QUE_PEND_8856 Navigator transmit queue pending event for indicated queue
270 QMSS_QUE_PEND_8857 Navigator transmit queue pending event for indicated queue
271 QMSS_QUE_PEND_8858 Navigator transmit queue pending event for indicated queue
272 QMSS_QUE_PEND_8859 Navigator transmit queue pending event for indicated queue
273 QMSS_QUE_PEND_8860 Navigator transmit queue pending event for indicated queue
274 QMSS_QUE_PEND_8861 Navigator transmit queue pending event for indicated queue
275 QMSS_QUE_PEND_8862 Navigator transmit queue pending event for indicated queue
276 QMSS_QUE_PEND_8863 Navigator transmit queue pending event for indicated queue
277 10GbE_LINK_INT0 10 Gigabit Ethernet subsystem MDIO interrupt (66AK2H14 only)
278 10GbE_LINK_INT1 10 Gigabit Ethernet subsystem MDIO interrupt (66AK2H14 only)
279 10GbE_USER_INT0 10 Gigabit Ethernet subsystem MDIO interrupt (66AK2H14 only)
280 10GbE_USER_INT1 10 Gigabit Ethernet subsystem MDIO interrupt (66AK2H14 only)
281 10GbE_MISC_INT 10 Gigabit Ethernet subsystem MDIO interrupt (66AK2H14 only)
282 10GbE_INT_PKTDMA_0 10 Gigabit Ethernet Packet DMA starvation interrupt
283 SEM_INT0 Semaphore interrupt
284 SEM_INT1 Semaphore interrupt
285 SEM_INT2 Semaphore interrupt
286 SEM_INT3 Semaphore interrupt
287 SEM_INT4 Semaphore interrupt
288 SEM_INT5 Semaphore interrupt
289 SEM_INT6 Semaphore interrupt
290 SEM_INT7 Semaphore interrupt
291 SEM_INT8 Semaphore interrupt
292 SEM_INT9 Semaphore interrupt
293 SEM_INT10 Semaphore interrupt
294 SEM_INT11 Semaphore interrupt
295 SEM_INT12 Semaphore interrupt
296 SEM_INT13 Semaphore interrupt
297 SEM_INT14 Semaphore interrupt
298 SEM_INT15 Semaphore interrupt
299 SEM_ERR8 Semaphore error interrupt
300 SEM_ERR9 Semaphore error interrupt
301 SEM_ERR10 Semaphore error interrupt
302 SEM_ERR11 Semaphore error interrupt
303 SEM_ERR12 Semaphore error interrupt
304 SEM_ERR13 Semaphore error interrupt
305 SEM_ERR14 Semaphore error interrupt
306 SEM_ERR15 Semaphore error interrupt
307 DDR3_1_ERR DDR3B error interrupt
308 HYPERLINK_1_INT HyperLink 1 interrupt
309 Reserved Reserved
310 Reserved Reserved
311 Reserved Reserved
312 Reserved Reserved
313 Reserved Reserved
314 Reserved Reserved
315 Reserved Reserved
316 Reserved Reserved
317 Reserved Reserved
318 Reserved Reserved
319 Reserved Reserved
320 Reserved Reserved
321 Reserved Reserved
322 Reserved Reserved
323 Reserved Reserved
324 Reserved Reserved
325 Reserved Reserved
326 Reserved Reserved
327 Reserved Reserved
328 Reserved Reserved
329 Reserved Reserved
330 Reserved Reserved
331 Reserved Reserved
332 Reserved Reserved
333 Reserved Reserved
334 Reserved Reserved
335 Reserved Reserved
336 Reserved Reserved
337 Reserved Reserved
338 Reserved Reserved
339 Reserved Reserved
340 Reserved Reserved
341 Reserved Reserved
342 Reserved Reserved
343 Reserved Reserved
344 Reserved Reserved
345 Reserved Reserved
346 Reserved Reserved
347 Reserved Reserved
348 Reserved Reserved
349 Reserved Reserved
350 Reserved Reserved
351 Reserved Reserved
352 Reserved Reserved
353 Reserved Reserved
354 Reserved Reserved
355 Reserved Reserved
356 Reserved Reserved
357 Reserved Reserved
358 Reserved Reserved
359 Reserved Reserved
360 Reserved Reserved
361 Reserved Reserved
362 PSC_ALLINT PSC interrupt
363 Reserved Reserved
364 Reserved Reserved
365 Reserved Reserved
366 Reserved Reserved
367 Reserved Reserved
368 Reserved Reserved
369 Reserved Reserved
370 Reserved Reserved
371 Reserved Reserved
372 MPU_9_INT MPU9 addressing violation interrupt and protection violation interrupt
373 MPU_10_INT MPU10 addressing violation interrupt and protection violation interrupt
374 MPU_11_INT MPU11 addressing violation interrupt and protection violation interrupt
375 TRACER_MSMC_4_INT Tracer sliding time window interrupt for MSMC SRAM Bank 4
376 TRACER_MSMC_5_INT Tracer sliding time window interrupt for MSMC SRAM Bank 4
377 TRACER_MSMC_6_INT Tracer sliding time window interrupt for MSMC SRAM Bank 4
378 TRACER_MSMC_7_INT Tracer sliding time window interrupt for MSMC SRAM Bank 4
379 TRACER_DDR_1_INT Tracer sliding time window interrupt for DDR3B
380 Reserved Reserved
381 Reserved Reserved
382 Reserved Reserved
383 Reserved Reserved
384 TRACER_SPI_ROM_EMIF_INT Tracer sliding time window interrupt for SPI/ROM/EMIF16 modules
385 Reserved Reserved
386 Reserved Reserved
387 TIMER_8_INTL Timer interrupt low
388 TIMER_8_INTH Timer interrupt high
389 TIMER_9_INTL Timer interrupt low
390 TIMER_9_INTH Timer interrupt high
391 TIMER_10_INTL Timer interrupt low
392 TIMER_10_INTH Timer interrupt high
393 TIMER_11_INTL Timer interrupt low
394 TIMER_11_INTH Timer interrupt high
395 TIMER_14_INTL Timer interrupt low
396 TIMER_14_INTH Timer interrupt high
397 TIMER_15_INTL Timer interrupt low
398 TIMER_15_INTH Timer interrupt high
399 USB_INT00 USB interrupt
400 USB_INT04 USB interrupt
401 USB_INT05 USB interrupt
402 USB_INT06 USB interrupt
403 USB_INT07 USB interrupt
404 USB_INT08 USB interrupt
405 USB_INT09 USB interrupt
406 USB_INT10 USB interrupt
407 USB_INT11 USB interrupt
408 USB_MISCINT USB miscellaneous interrupt
409 USB_OABSINT USB OABS interrupt
410 Reserved Reserved
411 Reserved Reserved
412 Reserved Reserved
413 Reserved Reserved
414 Reserved Reserved
415 Reserved Reserved
416 Reserved Reserved
417 Reserved Reserved
418 Reserved Reserved
419 Reserved Reserved
420 Reserved Reserved
421 Reserved Reserved
422 Reserved Reserved
423 Reserved Reserved
424 Reserved Reserved
425 Reserved Reserved
426 Reserved Reserved
427 Reserved Reserved
428 Reserved Reserved
429 Reserved Reserved
430 Reserved Reserved
431 Reserved Reserved
432 Reserved Reserved
433 Reserved Reserved
434 Reserved Reserved
435 Reserved Reserved
436 Reserved Reserved
437 Reserved Reserved
438 Reserved Reserved
439 Reserved Reserved
440 Reserved Reserved
441 Reserved Reserved
442 TETB_OVFLINT0 ETB0 overflow (emulation trace buffer)
443 TETB_UNFLINT0 ETB0 underflow
444 TETB_OVFLINT1 ETB1 overflow (emulation trace buffer)
445 TETB_UNFLINT1 ETB1 underflow
446 TETB_OVFLINT2 ETB2 overflow (emulation trace buffer)
447 TETB_UNFLINT2 ETB2 underflow
448 TETB_OVFLINT3 ETB3 overflow (emulation trace buffer)
449 TETB_UNFLINT3 ETB3 underflow
450 TETB_OVFLINT4 ETB4 overflow (emulation trace buffer)
451 TETB_UNFLINT4 ETB4 underflow
452 TETB_OVFLINT5 ETB5 overflow (emulation trace buffer)
453 TETB_UNFLINT5 ETB5 underflow
454 TETB_OVFLINT6 ETB6 overflow (emulation trace buffer)
455 TETB_UNFLINT6 ETB6 underflow
456 TETB_OVFLINT7 ETB7 overflow (emulation trace buffer)
457 TETB_UNFLINT7 ETB7 underflow
458 ARM_TBR_DMA ARM trace buffer
459 Reserved Reserved
460 Reserved Reserved
461 Reserved Reserved
462 Reserved Reserved
463 GPIO_INT0 GPIO interrupt
464 GPIO_INT1 GPIO interrupt
465 GPIO_INT2 GPIO interrupt
466 GPIO_INT3 GPIO interrupt
467 GPIO_INT4 GPIO interrupt
468 GPIO_INT5 GPIO interrupt
469 GPIO_INT6 GPIO interrupt
470 GPIO_INT7 GPIO interrupt
471 IPC_GR0 IPC interrupt generation
472 IPC_GR1 IPC interrupt generation
473 IPC_GR2 IPC interrupt generation
474 IPC_GR3 IPC interrupt generation
475 IPC_GR4 IPC interrupt generation
476 IPC_GR5 IPC interrupt generation
477 IPC_GR6 IPC interrupt generation
478 IPC_GR7 IPC interrupt generation
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