ZHCSBT2G November   2012  – October 2017 66AK2H06 , 66AK2H12 , 66AK2H14

PRODUCTION DATA.  

  1. 1 器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
      1. 1.3.1 KeyStone II 的增强功能
    4. 1.4 功能方框图
  2. 2 修订历史记录
  3. 3 Device Comparison
    1. 3.1 Related Products
  4. 4 Terminal Configuration and Functions
    1. 4.1 Package Terminals
    2. 4.2 Pin Map
    3. 4.3 Terminal Functions
    4. 4.4 Pullup/Pulldown Resistors
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Power Consumption Summary
    5. 5.5 Electrical Characteristics
    6. 5.6 Thermal Resistance Characteristics for PBGA Package [AAW]
    7. 5.7 Power Supply to Peripheral I/O Mapping
  6. 6 C66x CorePac
    1. 6.1 C66x DSP CorePac
    2. 6.2 Memory Architecture
      1. 6.2.1 L1P Memory
      2. 6.2.2 L1D Memory
      3. 6.2.3 L2 Memory
      4. 6.2.4 Multicore Shared Memory SRAM
      5. 6.2.5 L3 Memory
    3. 6.3 Memory Protection
    4. 6.4 Bandwidth Management
    5. 6.5 Power-Down Control
    6. 6.6 C66x CorePac Revision
      1. Table 6-2 CorePac Revision ID Register (MM_REVID) Field Descriptions
    7. 6.7 C66x CorePac Register Descriptions
  7. 7 ARM CorePac
    1. 7.1 Features
    2. 7.2 System Integration
    3. 7.3 ARM Cortex-A15 Processor
      1. 7.3.1 Overview
      2. 7.3.2 Features
      3. 7.3.3 ARM Interrupt Controller
      4. 7.3.4 Endianess
    4. 7.4 CFG Connection
    5. 7.5 Main TeraNet Connection
    6. 7.6 Clocking and Reset
      1. 7.6.1 Clocking
      2. 7.6.2 Reset
  8. 8 Memory, Interrupts, and EDMA for 66AK2Hxx
    1. 8.1 Memory Map Summary for 66AK2Hxx
    2. 8.2 Memory Protection Unit (MPU) for 66AK2Hxx
      1. 8.2.1 MPU Registers
        1. 8.2.1.1 MPU Register Map
        2. 8.2.1.2 Device-Specific MPU Registers
          1. 8.2.1.2.1 Configuration Register (CONFIG)
            1. Table 8-9 Configuration Register Field Descriptions
      2. 8.2.2 MPU Programmable Range Registers
        1. 8.2.2.1 Programmable Range n Start Address Register (PROGn_MPSAR)
          1. Table 8-10 Programmable Range n Start Address Register Field Descriptions
        2. 8.2.2.2 Programmable Range n - End Address Register (PROGn_MPEAR)
          1. Table 8-14 Programmable Range n End Address Register Field Descriptions
        3. 8.2.2.3 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPAR)
          1. Table 8-18 Programmable Range n Memory Protection Page Attribute Register Field Descriptions
    3. 8.3 Interrupts for 66AK2Hxx
      1. 8.3.1 Interrupt Sources and Interrupt Controller
      2. 8.3.2 CIC Registers
        1. 8.3.2.1 CIC0 Register Map
        2. 8.3.2.2 CIC1 Register Map
        3. 8.3.2.3 CIC2 Register Map
      3. 8.3.3 Inter-Processor Register Map
      4. 8.3.4 NMI and LRESET
    4. 8.4 Enhanced Direct Memory Access (EDMA3) Controller for 66AK2Hxx
      1. 8.4.1 EDMA3 Device-Specific Information
      2. 8.4.2 EDMA3 Channel Controller Configuration
      3. 8.4.3 EDMA3 Transfer Controller Configuration
      4. 8.4.4 EDMA3 Channel Synchronization Events
  9. 9 System Interconnect
    1. 9.1 Internal Buses and Switch Fabrics
    2. 9.2 Switch Fabric Connections Matrix - Data Space
    3. 9.3 TeraNet Switch Fabric Connections Matrix - Configuration Space
    4. 9.4 Bus Priorities
  10. 10Device Boot and Configuration
    1. 10.1 Device Boot
      1. 10.1.1 Boot Sequence
      2. 10.1.2 Boot Modes Supported
        1. 10.1.2.1 Boot Device Field
          1. Table 10-3 Boot Mode Pins: Boot Device Values
        2. 10.1.2.2 Device Configuration Field
          1. 10.1.2.2.1 Sleep Boot Mode Configuration
            1. Table 10-4 Sleep Boot Configuration Field Descriptions
          2. 10.1.2.2.2 I2C Boot Device Configuration
            1. 10.1.2.2.2.1 I2C Passive Mode
              1. Table 10-5 I2C Passive Mode Device Configuration Field Descriptions
            2. 10.1.2.2.2.2 I2C Master Mode
              1. Table 10-6 I2C Master Mode Device Configuration Field Descriptions
          3. 10.1.2.2.3 SPI Boot Device Configuration
            1. Table 10-7 SPI Device Configuration Field Descriptions
          4. 10.1.2.2.4 EMIF Boot Device Configuration
            1. Table 10-8 EMIF Boot Device Configuration Field Descriptions
          5. 10.1.2.2.5 NAND Boot Device Configuration
            1. Table 10-9 NAND Boot Device Configuration Field Descriptions
        3. 10.1.2.3 Serial Rapid I/O Boot Device Configuration
          1. Table 10-10 Serial Rapid I/O Boot Device Configuration Field Descriptions
        4. 10.1.2.4 Ethernet (SGMII) Boot Device Configuration
          1. Table 10-11 Ethernet (SGMII) Boot Device Configuration Field Descriptions
          2. 10.1.2.4.1   PCIe Boot Device Configuration
            1. Table 10-12 PCIe Boot Device Configuration Field Descriptions
          3. 10.1.2.4.2   HyperLink Boot Device Configuration
            1. Table 10-14 HyperLink Boot Device Configuration Field Descriptions
          4. 10.1.2.4.3   UART Boot Device Configuration
            1. Table 10-15 UART Boot Configuration Field Descriptions
        5. 10.1.2.5 Boot Parameter Table
          1. 10.1.2.5.1  EMIF16 Boot Parameter Table
          2. 10.1.2.5.2  SRIO Boot Parameter Table
          3. 10.1.2.5.3  Ethernet Boot Parameter Table
          4. 10.1.2.5.4  PCIe Boot Parameter Table
          5. 10.1.2.5.5  I2C Boot Parameter Table
          6. 10.1.2.5.6  SPI Boot Parameter Table
          7. 10.1.2.5.7  HyperLink Boot Parameter Table
          8. 10.1.2.5.8  UART Boot Parameter Table
          9. 10.1.2.5.9  NAND Boot Parameter Table
          10. 10.1.2.5.10 DDR3 Configuration Table
        6. 10.1.2.6 Second-Level Bootloaders
      3. 10.1.3 SoC Security
      4. 10.1.4 System PLL Settings
        1. 10.1.4.1 ARM CorePac System PLL Settings
    2. 10.2 Device Configuration
      1. 10.2.1 Device Configuration at Device Reset
      2. 10.2.2 Peripheral Selection After Device Reset
      3. 10.2.3 Device State Control Registers
        1. 10.2.3.1  Device Status (DEVSTAT) Register
          1. Table 10-31 Device Status Register Field Descriptions
        2. 10.2.3.2  Device Configuration Register
          1. Table 10-32 Device Configuration Register Field Descriptions
        3. 10.2.3.3  JTAG ID (JTAGID) Register Description
          1. Table 10-33 JTAG ID Register Field Descriptions
        4. 10.2.3.4  Kicker Mechanism (KICK0 and KICK1) Register
        5. 10.2.3.5  DSP Boot Address Register (DSP_BOOT_ADDRn)
          1. Table 10-1 DSP BOOT Address Register (DSP_BOOT_ADDRn)
        6. 10.2.3.6  LRESETNMI PIN Status (LRSTNMIPINSTAT) Register
          1. Table 10-35 LRESETNMI PIN Status Register Field Descriptions
        7. 10.2.3.7  LRESETNMI PIN Status Clear (LRSTNMIPINSTAT_CLR) Register
          1. Table 10-36 LRESETNMI PIN Status Clear Register Field Descriptions
        8. 10.2.3.8  Reset Status (RESET_STAT) Register
          1. Table 10-37 Reset Status Register Field Descriptions
        9. 10.2.3.9  Reset Status Clear (RESET_STAT_CLR) Register
          1. Table 10-38 Reset Status Clear Register Field Descriptions
        10. 10.2.3.10 Boot Complete (BOOTCOMPLETE) Register
          1. Table 10-39 Boot Complete Register Field Descriptions
        11. 10.2.3.11 Power State Control (PWRSTATECTL) Register
          1. Table 10-40 Power State Control Register Field Descriptions
        12. 10.2.3.12 NMI Event Generation to C66x CorePac (NMIGRx) Register
          1. Table 10-41 NMI Generation Register Field Descriptions
        13. 10.2.3.13 IPC Generation (IPCGRx) Registers
          1. Table 10-42 IPC Generation Registers Field Descriptions
        14. 10.2.3.14 IPC Acknowledgment (IPCARx) Registers
          1. Table 10-43 IPC Acknowledgment Registers Field Descriptions
        15. 10.2.3.15 IPC Generation Host (IPCGRH) Register
          1. Table 10-44 IPC Generation Registers Field Descriptions
        16. 10.2.3.16 IPC Acknowledgment Host (IPCARH) Register
          1. Table 10-45 IPC Acknowledgment Register Field Descriptions
        17. 10.2.3.17 Timer Input Selection Register (TINPSEL)
          1. Table 10-46 Timer Input Selection Field Description
        18. 10.2.3.18 Timer Output Selection Register (TOUTPSEL)
          1. Table 10-47 Timer Output Selection Register Field Descriptions
        19. 10.2.3.19 Reset Mux (RSTMUXx) Register
          1. Table 10-48 Reset Mux Register Field Descriptions
        20. 10.2.3.20 Device Speed (DEVSPEED) Register
          1. Table 10-49 Device Speed Register Field Descriptions
        21. 10.2.3.21 ARM Endian Configuration Register 0 (ARMENDIAN_CFGr_0), r=0..7
          1. Table 10-50 ARM Endian Configuration Register 0 Field Descriptions
        22. 10.2.3.22 ARM Endian Configuration Register 1 (ARMENDIAN_CFGr_1), r=0..7
          1. Table 10-51 ARM Endian Configuration Register 1 Field Descriptions
        23. 10.2.3.23 ARM Endian Configuration Register 2 (ARMENDIAN_CFGr_2), r=0..7
          1. Table 10-52 ARM Endian Configuration Register 2 Field Descriptions
        24. 10.2.3.24 Chip Miscellaneous Control (CHIP_MISC_CTL0) Register
          1. Table 10-53 Chip Miscellaneous Control Register Field Descriptions
        25. 10.2.3.25 Chip Miscellaneous Control (CHIP_MISC_CTL1) Register
          1. Table 10-54 Chip Miscellaneous Control Register Field Descriptions
        26. 10.2.3.26 System Endian Status Register (SYSENDSTAT)
          1. Table 10-55 System Endian Status Register Field Descriptions
        27. 10.2.3.27 SYNECLK_PINCTL Register
          1. Table 10-56 SYNECLK_PINCTL Register Field Descriptions
        28. 10.2.3.28 USB PHY Control (USB_PHY_CTLx) Registers
          1. Table 10-57 USB_PHY_CTL0 Register Field Descriptions
          2. Table 10-58 USB_PHY_CTL1 Register Field Descriptions
          3. Table 10-59 USB_PHY_CTL2 Register Field Descriptions
          4. Table 10-60 USB_PHY_CTL3 Register Field Descriptions
          5. Table 10-61 USB_PHY_CTL4 Register Field Descriptions
          6. Table 10-62 USB_PHY_CTL5 Register Field Descriptions
  11. 1166AK2Hxx Peripheral Information
    1. 11.1  Recommended Clock and Control Signal Transition Behavior
    2. 11.2  Power Supplies
      1. 11.2.1 Power-Up Sequencing
        1. 11.2.1.1 Core-Before-IO Power Sequencing
        2. 11.2.1.2 IO-Before-Core Power Sequencing
        3. 11.2.1.3 Prolonged Resets
        4. 11.2.1.4 Clocking During Power Sequencing
      2. 11.2.2 Power-Down Sequence
      3. 11.2.3 Power Supply Decoupling and Bulk Capacitor
      4. 11.2.4 SmartReflex
        1. Table 11-5 SmartReflex 4-Pin 6-bit VID Interface Switching Characteristics
    3. 11.3  Power Sleep Controller (PSC)
      1. 11.3.1 Power Domains
      2. 11.3.2 Clock Domains
      3. 11.3.3 PSC Register Memory Map
    4. 11.4  Reset Controller
      1. 11.4.1 Power-on Reset
      2. 11.4.2 Hard Reset
      3. 11.4.3 Soft Reset
      4. 11.4.4 Local Reset
      5. 11.4.5 ARM CorePac Reset
      6. 11.4.6 Reset Priority
      7. 11.4.7 Reset Controller Register
      8. 11.4.8 Reset Electrical Data and Timing
        1. Table 11-10 Reset Timing Requirements
        2. Table 11-11 Reset Switching Characteristics
        3. Table 11-12 Boot Configuration Timing Requirements
    5. 11.5  Main PLL, ARM PLL, DDR3A PLL, DDR3B PLL, PASS PLL and the PLL Controllers
      1. 11.5.1 Main PLL Controller Device-Specific Information
        1. 11.5.1.1 Internal Clocks and Maximum Operating Frequencies
        2. 11.5.1.2 Local Clock Dividers
        3. 11.5.1.3 Module Clock Input
        4. 11.5.1.4 Main PLL Controller Operating Modes
        5. 11.5.1.5 Main PLL Stabilization, Lock, and Reset Times
      2. 11.5.2 PLL Controller Memory Map
        1. 11.5.2.1 PLL Secondary Control Register (SECCTL)
          1. Table 11-16 PLL Secondary Control Register Field Descriptions
        2. 11.5.2.2 PLL Controller Divider Register (PLLDIV3 and PLLDIV4)
          1. Table 11-17 PLL Controller Divider Register Field Descriptions
        3. 11.5.2.3 PLL Controller Clock Align Control Register (ALNCTL)
          1. Table 11-18 PLL Controller Clock Align Control Register Field Descriptions
        4. 11.5.2.4 PLLDIV Divider Ratio Change Status Register (DCHANGE)
          1. Table 11-19 PLLDIV Divider Ratio Change Status Register Field Descriptions
        5. 11.5.2.5 SYSCLK Status Register (SYSTAT)
          1. Table 11-20 SYSCLK Status Register Field Descriptions
        6. 11.5.2.6 Reset Type Status Register (RSTYPE)
          1. Table 11-21 Reset Type Status Register Field Descriptions
        7. 11.5.2.7 Reset Control Register (RSTCTRL)
          1. Table 11-22 Reset Control Register Field Descriptions
        8. 11.5.2.8 Reset Configuration Register (RSTCFG)
          1. Table 11-23 Reset Configuration Register Field Descriptions
        9. 11.5.2.9 Reset Isolation Register (RSISO)
          1. Table 11-24 Reset Isolation Register Field Descriptions
      3. 11.5.3 Main PLL Control Registers
        1. Table 11-25 Main PLL Control Register 0 (MAINPLLCTL0) Field Descriptions
        2. Table 11-26 Main PLL Control Register 1 (MAINPLLCTL1) Field Descriptions
      4. 11.5.4 ARM PLL Control Registers
        1. Table 11-27 ARM PLL Control Register 0 Field Descriptions
        2. Table 11-28 ARM PLL Control Register 1 Field Descriptions
      5. 11.5.5 Main PLL Controller, ARM, SRIO, HyperLink, PCIe, USB Clock Input Electrical Data and Timing
        1. Table 11-29 Main PLL Controller, ARM, SRIO, HyperLink, PCIe, USB Clock Input Timing Requirements
    6. 11.6  DDR3A PLL and DDR3B PLL
      1. 11.6.1 DDR3A PLL and DDR3B PLL Control Registers
        1. Table 11-30 DDR3A PLL and DDR3B PLL Control Register 0 Field Descriptions
        2. Table 11-31 DDR3A PLL and DDR3B PLL Control Register 1 Field Descriptions
      2. 11.6.2 DDR3A PLL and DDR3B PLL Device-Specific Information
      3. 11.6.3 DDR3 PLL Input Clock Electrical Data and Timing
        1. Table 11-32 DDR3 PLL DDRCLK(N|P) Timing Requirements
    7. 11.7  PASS PLL
      1. 11.7.1 PASS PLL Local Clock Dividers
      2. 11.7.2 PASS PLL Control Registers
        1. Table 11-33 PASS PLL Control Register 0 Field Descriptions (PASSPLLCTL0)
        2. Table 11-34 PASS PLL Control Register 1 Field Descriptions (PASSPLLCTL1)
      3. 11.7.3 PASS PLL Device-Specific Information
      4. 11.7.4 PASS PLL Input Clock Electrical Data and Timing
        1. Table 11-35 PASS PLL Timing Requirements
    8. 11.8  External Interrupts
      1. 11.8.1 External Interrupts Electrical Data and Timing
        1. Table 11-36 NMI and LRESET Timing Requirements
    9. 11.9  DDR3A and DDR3B Memory Controllers
      1. 11.9.1 DDR3 Memory Controller Device-Specific Information
      2. 11.9.2 DDR3 Slew Rate Control
      3. 11.9.3 DDR3 Memory Controller Electrical Data and Timing
    10. 11.10 I2C Peripheral
      1. 11.10.1 I2C Device-Specific Information
      2. 11.10.2 I2C Peripheral Register Description
      3. 11.10.3 I2C Electrical Data and Timing
        1. Table 11-38 I2C Timing Requirements
        2. Table 11-39 I2C Switching Characteristics
    11. 11.11 SPI Peripheral
      1. 11.11.1 SPI Electrical Data and Timing
        1. Table 11-40 SPI Timing Requirements
        2. Table 11-41 SPI Switching Characteristics
    12. 11.12 HyperLink Peripheral
      1. Table 11-42 HyperLink Peripheral Timing Requirements
      2. Table 11-43 HyperLink Peripheral Switching Characteristics
    13. 11.13 UART Peripheral
      1. Table 11-44 UART Timing Requirements
      2. Table 11-45 UART Switching Characteristics
    14. 11.14 PCIe Peripheral
    15. 11.15 Packet Accelerator
    16. 11.16 Security Accelerator
    17. 11.17 Network Coprocessor Gigabit Ethernet (GbE) Switch Subsystem
      1. Table 11-46 MACID1 Register Field Descriptions
      2. Table 11-47 MACID2 Register Field Descriptions
      3. Table 11-48 RFTCLK Select Register Field Descriptions
    18. 11.18 SGMII and XFI Management Data Input/Output (MDIO)
      1. Table 11-49 MDIO Timing Requirements
      2. Table 11-50 MDIO Switching Characteristics
    19. 11.19 Ten-Gigabit Ethernet (10GbE) Switch Subsystem
      1. 11.19.1 10GbE Supported Features
    20. 11.20 Timers
      1. 11.20.1 Timers Device-Specific Information
      2. 11.20.2 Timers Electrical Data and Timing
        1. Table 11-51 Timer Input Timing Requirements
        2. Table 11-52 Timer Output Switching Characteristics
    21. 11.21 Serial RapidIO (SRIO) Port
      1. 11.21.1 Serial RapidIO Device-Specific Information
    22. 11.22 General-Purpose Input/Output (GPIO)
      1. 11.22.1 GPIO Device-Specific Information
      2. 11.22.2 GPIO Peripheral Register Description
      3. 11.22.3 GPIO Electrical Data and Timing
        1. Table 11-54 GPIO Input Timing Requirements
        2. Table 11-55 GPIO Output Switching Characteristics
    23. 11.23 Semaphore2
    24. 11.24 Universal Serial Bus 3.0 (USB 3.0)
    25. 11.25 EMIF16 Peripheral
      1. 11.25.1 EMIF16 Electrical Data and Timing
        1. Table 11-56 EMIF16 Asynchronous Memory Timing Requirements
    26. 11.26 Emulation Features and Capability
      1. 11.26.1 Chip-Level Features
        1. 11.26.1.1 ARM Subsystem Features
        2. 11.26.1.2 DSP Features
      2. 11.26.2 ICEPick Module
        1. 11.26.2.1 ICEPick Dynamic Tap Insertion
    27. 11.27 Debug Port (EMUx)
      1. 11.27.1 Concurrent Use of Debug Port
      2. 11.27.2 Master ID for Hardware and Software Messages
      3. 11.27.3 SoC Cross-Triggering Connection
      4. 11.27.4 Peripherals-Related Debug Requirement
      5. 11.27.5 Advanced Event Triggering (AET)
      6. 11.27.6 Trace
        1. 11.27.6.1 Trace Electrical Data and Timing
          1. Table 11-66 Trace Switching Characteristics
      7. 11.27.7 IEEE 1149.1 JTAG
        1. 11.27.7.1 IEEE 1149.1 JTAG Compatibility Statement
        2. 11.27.7.2 JTAG Electrical Data and Timing
          1. Table 11-67 JTAG Test Port Timing Requirements
          2. Table 11-68 JTAG Test Port Switching Characteristics
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Tools and Software
    3. 12.3 Documentation Support
    4. 12.4 Related Links
    5. 12.5 Community Resources
    6. 12.6 商标
    7. 12.7 静电放电警告
    8. 12.8 术语表
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Packaging Information

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8.4.4 EDMA3 Channel Synchronization Events

The EDMA3 supports up to 64 DMA channels for all EDMA3CC that can be used to service system peripherals and to move data between system memories. DMA channels can be triggered by synchronization events generated by system peripherals. The following tables list the source of the synchronization event associated with each of the EDMA3CC DMA channels. On the 66AK2Hxx, the association of each synchronization event and DMA channel is fixed and cannot be reprogrammed.

For more detailed information on the EDMA3 module and how EDMA3 events are enabled, captured, processed, prioritized, linked, chained, and cleared, and so forth, see the KeyStone Architecture Enhanced Direct Memory Access 3 (EDMA3) User's Guide.

Table 8-34 EDMA3CC0 Events for 66AK2Hxx

EVENT NO. EVENT NAME DESCRIPTION
0 TIMER_8_INTL Timer interrupt low
1 TIMER_8_INTH Timer interrupt high
2 TIMER_9_INTL Timer interrupt low
3 TIMER_9_INTH Timer interrupt high
4 TIMER_10_INTL Timer interrupt low
5 TIMER_10_INTH Timer interrupt high
6 TIMER_11_INTL Timer interrupt low
7 TIMER_11_INTH Timer interrupt high
8 CIC_2_OUT66 CIC2 Interrupt Controller output
9 CIC_2_OUT67 CIC2 Interrupt Controller output
10 CIC_2_OUT68 CIC2 Interrupt Controller output
11 CIC_2_OUT69 CIC2 Interrupt Controller output
12 CIC_2_OUT70 CIC2 Interrupt Controller output
13 CIC_2_OUT71 CIC2 Interrupt Controller output
14 CIC_2_OUT72 CIC2 Interrupt Controller output
15 CIC_2_OUT73 CIC2 Interrupt Controller output
16 GPIO_INT8 GPIO interrupt
17 GPIO_INT9 GPIO interrupt
18 GPIO_INT10 GPIO interrupt
19 GPIO_INT11 GPIO interrupt
20 GPIO_INT12 GPIO interrupt
21 GPIO_INT13 GPIO interrupt
22 GPIO_INT14 GPIO interrupt
23 GPIO_INT15 GPIO interrupt
24 TIMER_4_INTL Timer interrupt low(1)
25 TIMER_4_INTH Timer interrupt high(1)
26 TIMER_5_INTL Timer interrupt low(1)
27 TIMER_5_INTH Timer interrupt high(1)
28 TIMER_6_INTL Timer interrupt low(1)
29 TIMER_6_INTH Timer interrupt high(1)
30 TIMER_7_INTL Timer interrupt low(1)
31 TIMER_7_INTH Timer interrupt high(1)
32 GPIO_INT0 GPIO interrupt
33 GPIO_INT1 GPIO interrupt
34 GPIO_INT2 GPIO interrupt
35 GPIO_INT3 GPIO interrupt
36 GPIO_INT4 GPIO interrupt
37 GPIO_INT5 GPIO interrupt
38 GPIO_INT6 GPIO interrupt
39 GPIO_INT7 GPIO interrupt
40 TIMER_0_INTL Timer interrupt low
41 TIMER_0_INTH Timer interrupt high
42 TIMER_1_INTL Timer interrupt low
43 TIMER_1_INTH Timer interrupt high
44 TIMER_2_INTL Timer interrupt low
45 TIMER_2_INTH Timer interrupt high
46 TIMER_3_INTL Timer interrupt low
47 TIMER_3_INTH Timer interrupt high
48 SRIO_INTDST0 SRIO interrupt
49 SRIO_INTDST1 SRIO interrupt
50 SRIO_INTDST2 SRIO interrupt
51 SRIO_INTDST3 SRIO interrupt
52 SRIO_INTDST4 SRIO interrupt
53 SRIO_INTDST5 SRIO interrupt
54 SRIO_INTDST6 SRIO interrupt
55 SRIO_INTDST7 SRIO interrupt
56 Reserved Reserved
57 Reserved Reserved
58 Reserved Reserved
59 Reserved Reserved
60 Reserved Reserved
61 Reserved Reserved
62 Reserved Reserved
63 Reserved Reserved
(1) 66AK2H12/14 only.

Table 8-35 EDMA3CC1 Events for 66AK2Hxx

EVENT NO. EVENT NAME DESCRIPTION
0 SPI_0_INT0 SPI0 interrupt
1 SPI_0_INT1 SPI0 interrupt
2 SPI_0_XEVT SPI0 transmit event
3 SPI_0_REVT SPI0 receive event
4 SEM_INT8 Semaphore interrupt
5 SEM_INT9 Semaphore interrupt
6 GPIO_INT0 GPIO interrupt
7 GPIO_INT1 GPIO interrupt
8 GPIO_INT2 GPIO interrupt
9 GPIO_INT3 GPIO interrupt
10 Reserved Reserved
11 Reserved Reserved
12 Reserved Reserved
13 Reserved Reserved
14 SEM_INT0 Semaphore interrupt
15 SEM_INT1 Semaphore interrupt
16 SEM_INT2 Semaphore interrupt
17 SEM_INT3 Semaphore interrupt
18 SEM_INT4 Semaphore interrupt
19 SEM_INT5 Semaphore interrupt
20 SEM_INT6 Semaphore interrupt
21 SEM_INT7 Semaphore interrupt
22 TIMER_8_INTL Timer interrupt low
23 TIMER_8_INTH Timer interrupt high
24 TIMER_9_INTL Timer interrupt low
25 TIMER_9_INTH Timer interrupt high
26 TIMER_10_INTL Timer interrupt low
27 TIMER_10_INTH Timer interrupt high
28 TIMER_11_INTL Timer interrupt low
29 TIMER_11_INTH Timer interrupt high
30 TIMER_12_INTL Timer interrupt low
31 TIMER_12_INTH Timer interrupt high
32 TIMER_13_INTL Timer interrupt low
33 TIMER_13_INTH Timer interrupt high
34 TIMER_14_INTL Timer interrupt low
35 TIMER_14_INTH Timer interrupt high
36 TIMER_15_INTL Timer interrupt low
37 TIMER_15_INTH Timer interrupt high
38 SEM_INT10 Semaphore interrupt
39 SEM_INT11 Semaphore interrupt
40 SEM_INT12 Semaphore interrupt
41 SEM_INT13 Semaphore interrupt
42 CIC_2_OUT0 CIC2 Interrupt Controller output
43 CIC_2_OUT1 CIC2 Interrupt Controller output
44 CIC_2_OUT2 CIC2 Interrupt Controller output
45 CIC_2_OUT3 CIC2 Interrupt Controller output
46 CIC_2_OUT4 CIC2 Interrupt Controller output
47 CIC_2_OUT5 CIC2 Interrupt Controller output
48 CIC_2_OUT6 CIC2 Interrupt Controller output
49 CIC_2_OUT7 CIC2 Interrupt Controller output
50 CIC_2_OUT8 CIC2 Interrupt Controller output
51 Reserved Reserved
52 Reserved Reserved
53 I2C_0_REVT I2C0 receive
54 I2C_0_XEVT I2C0 transmit
55 CIC_2_OUT13 CIC2 Interrupt Controller output
56 CIC_2_OUT14 CIC2 Interrupt Controller output
57 CIC_2_OUT15 CIC2 Interrupt Controller output
58 CIC_2_OUT16 CIC2 Interrupt Controller output
59 CIC_2_OUT17 CIC2 Interrupt Controller output
60 CIC_2_OUT18 CIC2 Interrupt Controller output
61 CIC_2_OUT19 CIC2 Interrupt Controller output
62 Reserved Reserved
63 Reserved Reserved

Table 8-36 EDMA3CC2 Events for 66AK2Hxx

EVENT NO. EVENT NAME DESCRIPTION
0 Reserved Reserved
1 Reserved Reserved
2 Reserved Reserved
3 Reserved Reserved
4 Reserved Reserved
5 Reserved Reserved
6 TETB_FULLINT4 TETB4 is full
7 TETB_HFULLINT4 TETB4 is half full
8 TETB_FULLINT5 TETB5 is full
9 TETB_HFULLINT5 TETB5 is half full
10 TETB_FULLINT6 TETB6 is full
11 TETB_HFULLINT6 TETB6 is half full
12 TETB_FULLINT7 TETB7 is full
13 TETB_HFULLINT7 TETB7 is half full
14 SRIO_INTDST0 SRIO interrupt
15 SRIO_INTDST1 SRIO interrupt
16 SRIO_INTDST2 SRIO interrupt
17 SRIO_INTDST3 SRIO interrupt
18 SRIO_INTDST4 SRIO interrupt
19 SRIO_INTDST5 SRIO interrupt
20 SRIO_INTDST6 SRIO interrupt
21 SRIO_INTDST7 SRIO interrupt
22 Reserved Reserved
23 Reserved Reserved
24 Reserved Reserved
25 Reserved Reserved
26 GPIO_INT0 GPIO interrupt
27 GPIO_INT1 GPIO interrupt
28 GPIO_INT2 GPIO interrupt
29 GPIO_INT3 GPIO interrupt
30 GPIO_INT4 GPIO interrupt
31 GPIO_INT5 GPIO interrupt
32 GPIO_INT6 GPIO interrupt
33 GPIO_INT7 GPIO interrupt
34 Reserved Reserved
35 Reserved Reserved
36 Reserved Reserved
37 Reserved Reserved
38 CIC_2_OUT48 CIC2 Interrupt Controller output
39 Reserved Reserved
40 UART_0_URXEVT UART0 receive event
41 UART_0_UTXEVT UART0 transmit event
42 CIC_2_OUT22 CIC2 Interrupt Controller output
43 CIC_2_OUT23 CIC2 Interrupt Controller output
44 CIC_2_OUT24 CIC2 Interrupt Controller output
45 CIC_2_OUT25 CIC2 Interrupt Controller output
46 CIC_2_OUT26 CIC2 Interrupt Controller output
47 CIC_2_OUT27 CIC2 Interrupt Controller output
48 CIC_2_OUT28 CIC2 Interrupt Controller output
49 SPI_0_XEVT SPI0 transmit event
50 SPI_0_REVT SPI0 receive event
51 Reserved Reserved
52 Reserved Reserved
53 Reserved Reserved
54 Reserved Reserved
55 Reserved Reserved
56 Reserved Reserved
57 Reserved Reserved
58 Reserved Reserved
59 Reserved Reserved
60 Reserved Reserved
61 Reserved Reserved
62 Reserved Reserved
63 Reserved Reserved

Table 8-37 EDMA3CC3 Events for 66AK2Hxx

EVENT NO. EVENT NAME DESCRIPTION
0 SPI_2_INT0 SPI2 interrupt
1 SPI_2_INT1 SPI2 interrupt
2 SPI_2_XEVT SPI2 transmit event
3 SPI_2_REVT SPI2 receive event
4 I2C_2_REVT I2C2 receive
5 I2C_2_XEVT I2C2 transmit
6 UART_1_URXEVT UART1 receive event
7 UART_1_UTXEVT UART1 transmit event
8 SPI_1_INT0 SPI1 interrupt
9 SPI_1_INT1 SPI1 interrupt
10 SPI_1_XEVT SPI1 transmit event
11 SPI_1_REVT SPI1 receive event
12 I2C_0_REVT I2C0 receive
13 I2C_0_XEVT I2C0 transmit
14 I2C_1_REVT I2C1 receive
15 I2C_1_XEVT I2C1 transmit
16 SRIO_INTDST0 SRIO interrupt
17 SRIO_INTDST1 SRIO interrupt
18 SRIO_INTDST2 SRIO interrupt
19 SRIO_INTDST3 SRIO interrupt
20 SRIO_INTDST4 SRIO interrupt
21 SRIO_INTDST5 SRIO interrupt
22 SRIO_INTDST6 SRIO interrupt
23 SRIO_INTDST7 SRIO interrupt
24 Reserved Reserved
25 Reserved Reserved
26 Reserved Reserved
27 Reserved Reserved
28 Reserved Reserved
29 Reserved Reserved
30 Reserved Reserved
31 Reserved Reserved
32 TETB_FULLINT0 TETB0 is full
33 TETB_HFULLINT0 TETB0 is half full
34 TETB_FULLINT1 TETB1 is full
35 TETB_HFULLINT1 TETB1 is half full
36 TETB_FULLINT2 TETB2 is full
37 TETB_HFULLINT2 TETB2 is half full
38 TETB_FULLINT3 TETB3 is full
39 TETB_HFULLINT3 TETB3 is half full
40 Reserved Reserved
41 Reserved Reserved
42 Reserved Reserved
43 Reserved Reserved
44 Reserved Reserved
45 Reserved Reserved
46 Reserved Reserved
47 Reserved Reserved
48 Reserved Reserved
49 Reserved Reserved
50 Reserved Reserved
51 Reserved Reserved
52 Reserved Reserved
53 Reserved Reserved
54 Reserved Reserved
55 Reserved Reserved
56 CIC_2_OUT57 CIC2 Interrupt Controller output
57 CIC_2_OUT50 CIC2 Interrupt Controller output
58 CIC_2_OUT51 CIC2 Interrupt Controller output
59 CIC_2_OUT52 CIC2 Interrupt Controller output
60 CIC_2_OUT53 CIC2 Interrupt Controller output
61 CIC_2_OUT54 CIC2 Interrupt Controller output
62 CIC_2_OUT55 CIC2 Interrupt Controller output
63 CIC_2_OUT56 CIC2 Interrupt Controller output

Table 8-38 EDMA3CC4 Events for 66AK2Hxx

EVENT NO. EVENT NAME DESCRIPTION
0 GPIO_INT16 GPIO interrupt
1 GPIO_INT17 GPIO interrupt
2 GPIO_INT18 GPIO interrupt
3 GPIO_INT19 GPIO interrupt
4 GPIO_INT20 GPIO interrupt
5 GPIO_INT21 GPIO interrupt
6 GPIO_INT22 GPIO interrupt
7 GPIO_INT23 GPIO interrupt
8 Reserved Reserved
9 Reserved Reserved
10 Reserved Reserved
11 Reserved Reserved
12 Reserved Reserved
13 Reserved Reserved
14 Reserved Reserved
15 Reserved Reserved
16 Reserved Reserved
17 Reserved Reserved
18 Reserved Reserved
19 Reserved Reserved
20 Reserved Reserved
21 Reserved Reserved
22 Reserved Reserved
23 Reserved Reserved
24 TIMER_8_INTL Timer interrupt low
25 TIMER_8_INTH Timer interrupt high
26 TIMER_14_INTL Timer interrupt low
27 TIMER_14_INTH Timer interrupt high
28 TIMER_15_INTL Timer interrupt low
29 TIMER_15_INTH Timer interrupt high
30 DBGTBR_DMAINT Debug trace buffer (TBR) DMA event
31 ARM_TBR_DMA ARM trace buffer (TBR) DMA event
32 QMSS_QUE_PEND_658 Navigator transmit queue pending event for indicated queue
33 QMSS_QUE_PEND_659 Navigator transmit queue pending event for indicated queue
34 QMSS_QUE_PEND_660 Navigator transmit queue pending event for indicated queue
35 QMSS_QUE_PEND_661 Navigator transmit queue pending event for indicated queue
36 QMSS_QUE_PEND_662 Navigator transmit queue pending event for indicated queue
37 QMSS_QUE_PEND_663 Navigator transmit queue pending event for indicated queue
38 QMSS_QUE_PEND_664 Navigator transmit queue pending event for indicated queue
39 QMSS_QUE_PEND_665 Navigator transmit queue pending event for indicated queue
40 QMSS_QUE_PEND_8736 Navigator transmit queue pending event for indicated queue
41 QMSS_QUE_PEND_8737 Navigator transmit queue pending event for indicated queue
42 QMSS_QUE_PEND_8738 Navigator transmit queue pending event for indicated queue
43 QMSS_QUE_PEND_8739 Navigator transmit queue pending event for indicated queue
44 QMSS_QUE_PEND_8740 Navigator transmit queue pending event for indicated queue
45 QMSS_QUE_PEND_8741 Navigator transmit queue pending event for indicated queue
46 QMSS_QUE_PEND_8742 Navigator transmit queue pending event for indicated queue
47 QMSS_QUE_PEND_8743 Navigator transmit queue pending event for indicated queue
48 ARM_NCNTVIRQ3 ARM virtual timer interrupt for core 3
49 ARM_NCNTVIRQ2 ARM virtual timer interrupt for core 2
50 ARM_NCNTVIRQ1 ARM virtual timer interrupt for core 1
51 ARM_NCNTVIRQ0 ARM virtual timer interrupt for core 0
52 ARM_NCNTPNSIRQ3 ARM non secure timer interrupt for core 3
53 ARM_NCNTPNSIRQ2 ARM non secure timer interrupt for core 2
54 ARM_NCNTPNSIRQ1 ARM non secure timer interrupt for core 1
55 ARM_NCNTPNSIRQ0 ARM non secure timer interrupt for core 0
56 CIC_2_OUT82 CIC2 Interrupt Controller output
57 CIC_2_OUT83 CIC2 Interrupt Controller output
58 CIC_2_OUT84 CIC2 Interrupt Controller output
59 CIC_2_OUT85 CIC2 Interrupt Controller output
60 CIC_2_OUT86 CIC2 Interrupt Controller output
61 CIC_2_OUT87 CIC2 Interrupt Controller output
62 CIC_2_OUT88 CIC2 Interrupt Controller output
63 CIC_2_OUT89 CIC2 Interrupt Controller output
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