SNAS279F April 2005 – July 2016 ADC084S021
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Detailed Description
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(2)(3)| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| Supply voltage, VA | –0.3 | 6.5 | V | |
| Voltage on any pin to GND | –0.3 | VA + 0.3 | V | |
| Input current at any pin(4) | ±10 | mA | ||
| Package input current(4) | ±20 | mA | ||
| Power consumption at TA = 25°C | See (5) | |||
| Junction temperature, TJ | 150 | °C | ||
| Storage temperature, Tstg | –65 | 150 | °C | |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are measured with respect to GND = 0 V (unless otherwise specified).
(3) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/Distributors for availability and specifications.
(4) When the input voltage at any pin exceeds the power supply (that is, VIN < GND or VIN > VA), the current at that pin must be limited to 10 mA. The 20-mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two. The Absolute Maximum Ratings does not apply to the VA pin. The current into the VA pin is limited by the analog supply voltage specification.
(5) The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (RθJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA) / RθJA. The values for maximum power dissipation listed above is reached only when the device is operated in a severe fault condition (that is, when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Such conditions must always be avoided.
7.2 ESD Ratings
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)(2) | ±2500 | V |
| Machine model (MM)(3) | ±250 | |||
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) Human-body model is 100-pF capacitor discharged through a 1.5-kΩ resistor.
(3) Machine model is 220-pF discharged through 0 Ω.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)(2)| MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|
| VA | Supply voltage | 2.7 | 5.25 | V | |
| Digital input voltage | –0.3 | VA | V | ||
| Analog input voltage | 0 | VA | V | ||
| Clock frequency | 0.8 | 3.2 | MHz | ||
| TA | Operating temperature | –40 | 85 | °C | |
(1) Recommended Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
(2) All voltages are measured with respect to GND = 0 V (unless otherwise specified).
7.4 Thermal Information
| THERMAL METRIC(1)(2) | ADC084S021 | UNIT | |
|---|---|---|---|
| DGK (VSSOP) | |||
| 10 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 190 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 61.3 | °C/W |
| RθJB | Junction-to-board thermal resistance | 90 | °C/W |
| ψJT | Junction-to-top characterization parameter | 7.6 | °C/W |
| ψJB | Junction-to-board characterization parameter | 88.6 | °C/W |
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
(2) Reflow temperature profiles are different for lead-free and non-lead-free packages.
7.5 Electrical Characteristics
VA = 2.7 V to 5.25 V, GND = 0 V, fSCLK = 0.8 MHz to 3.2 MHz, fSAMPLE = 50 ksps to 200 ksps, CL = 50 pF, and TA = 25°C (unless otherwise noted)(1)| PARAMETER | TEST CONDITIONS | MIN(2) | TYP | MAX(2) | UNIT | |
|---|---|---|---|---|---|---|
| STATIC CONVERTER CHARACTERISTICS | ||||||
| Resolution with no missing codes | 8 | Bits | ||||
| INL | Integral non-linearity | ±0.04 | ±0.2 | LSB | ||
| DNL | Differential non-linearity | ±0.04 | ±0.2 | LSB | ||
| VOFF | Offset error | 0.52 | ±0.7 | LSB | ||
| OEM | Channel-to-channel offset error match | ±0.01 | ±0.3 | LSB | ||
| FSE | Full-scale error | 0.51 | ±0.7 | LSB | ||
| FSEM | Channel-to-channel full-scale error match | 0.01 | ±0.3 | LSB | ||
| DYNAMIC CONVERTER CHARACTERISTICS | ||||||
| SINAD | Signal-to-noise plus distortion ratio | VA = 2.7 V to 5.25 V fIN = 39.9 kHz, –0.02 dBFS |
49.1 | 49.6 | dB | |
| SNR | Signal-to-noise ratio | VA = 2.7 V to 5.25 V fIN = 39.9 kHz, –0.02 dBFS |
49.2 | 49.6 | dB | |
| THD | Total harmonic distortion | VA = 2.7 V to 5.25 V fIN = 39.9 kHz, –0.02 dBFS |
−76 | −62 | dB | |
| SFDR | Spurious-free dynamic range | VA = 2.7 V to 5.25 V fIN = 39.9 kHz, −0.02 dBFS |
63 | 68 | dB | |
| ENOB | Effective number of bits | VA = 2.7 V to 5.25 V fIN = 39.9 kHz, –0.02 dBFS |
7.9 | Bits | ||
| Channel-to-channel crosstalk | VA = 5.25 V fIN = 39.9 kHz |
−73 | dB | |||
| IMD | Intermodulation distortion, second order terms | VA = 5.25 V fa = 40.161 kHz, fb = 41.015 kHz |
−78 | dB | ||
| Intermodulation distortion, third order terms | VA = 5.25 V fa = 40.161 kHz, fb = 41.015 kHz |
−73 | ||||
| FPBW | Full power bandwidth, –3 dB | VA = 5 V | 11 | MHz | ||
| VA = 3 V | 8 | |||||
| ANALOG INPUT CHARACTERISTICS | ||||||
| VIN | Input range | 0 to VA | V | |||
| IDCL | DC leakage current | ±1 | µA | |||
| CINA | Input capacitance | Track mode | 33 | pF | ||
| Hold mode | 3 | |||||
| DIGITAL INPUT CHARACTERISTICS | ||||||
| VIH | Input high voltage | VA = 5.25 V | 2.4 | V | ||
| VA = 3.6 V | 2.1 | |||||
| VIL | Input low voltage | 0.8 | V | |||
| IIN | Input current | VIN = 0 V or VA | ±10 | µA | ||
| CIND | Digital input capacitance | 2 | 4 | pF | ||
| DIGITAL OUTPUT CHARACTERISTICS | ||||||
| VOH | Output high voltage | ISOURCE = 200 µA | VA – 0.5 | VA – 0.03 | V | |
| ISOURCE = 1 mA | VA – 0.1 | |||||
| VOL | Output low voltage | ISINK = 200 µA | 0.03 | 0.4 | V | |
| ISINK = 1 mA | 0.1 | |||||
| IOZH, IOZL | TRI-STATE® leakage current | ±1 | µA | |||
| COUT | TRI-STATE® output capacitance | 2 | 4 | pF | ||
| Output coding | Straight (natural) binary | |||||
| POWER SUPPLY CHARACTERISTICS (CL = 10 pF) | ||||||
| VA | Supply voltage | 2.7 | 5.25 | V | ||
| IA | Supply current, normal mode (operational, CS low) |
VA = 5.25 V, fSAMPLE = 200 ksps, fIN = 40 kHz |
1.1 | 1.7 | mA | |
| VA = 3.6 V, fSAMPLE = 200 ksps, fIN = 40 kHz |
0.45 | 0.8 | ||||
| Supply current, shutdown (CS high) |
VA = 5.25 V, fSAMPLE = 0 ksps |
200 | nA | |||
| VA = 3.6 V, fSAMPLE = 0 ksps |
200 | |||||
| PD | Power consumption, normal mode (operational, CS low) |
VA = 5.25 V | 5.8 | 8.9 | mW | |
| VA = 3.6 V | 1.6 | 2.9 | ||||
| Power consumption, shutdown (CS high) |
VA = 5.25 V | 1.05 | µW | |||
| VA = 3.6 V | 0.72 | |||||
| AC ELECTRICAL CHARACTERISTICS | ||||||
| fSCLK | Clock frequency | (3) | 0.8 | 3.2 | MHz | |
| fS | Sample rate | (3) | 50 | 200 | ksps | |
| tCONV | Conversion time | 13 | SCLK cycles | |||
| DC | SCLK duty cycle | fSCLK = 3.2 MHz | 30% | 50% | 70% | |
| tACQ | Track or hold acquisition time | Full-scale step input | 3 | SCLK cycles | ||
| Throughput time | Acquisition time + conversion time | 16 | SCLK cycles | |||
(1) Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).
(2) Minimum and maximum specification limits are specified by design, test, or statistical analysis.
(3) This is the frequency range over which the electrical performance is ensured. The device is functional over a wider range which is specified in Recommended Operating Conditions.
7.6 Timing Requirements
VA = 2.7 V to 5.25 V, GND = 0 V, fSCLK = 0.8 MHz to 3.2 MHz, fSAMPLE = 50 ksps to 200 ksps, CL = 50 pF, and TA = 25°C (unless otherwise noted)(1)| PARAMETER | TEST CONDITIONS | MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| tCSU | Setup time SCLK high to CS falling edge(2) | VA = 3 V | 10 | ns | |||
| VA = 5 V | 10 | –0.5 | |||||
| tCLH | Hold time SCLK low to CS falling edge(2) | VA = 3 V | 10 | 4.5 | ns | ||
| VA = 5 V | 10 | 1.5 | |||||
| tEN | Delay from CS until DOUT active | VA = 3 V | 4 | 30 | ns | ||
| VA = 5 V | 2 | 30 | |||||
| tACC | Data access time after SCLK falling edge | VA = 3 V | 16.5 | 30 | ns | ||
| VA = 5 V | 15 | 30 | |||||
| tSU | Data setup time prior to SCLK rising edge | 10 | 3 | ns | |||
| tH | Data valid SCLK hold time | 10 | 3 | ns | |||
| tCH | SCLK high pulse width | 0.3 × tSCLK | 0.5 × tSCLK | ns | |||
| tCL | SCLK low pulse width | 0.3 × tSCLK | 0.5 × tSCLK | ns | |||
| tDIS | CS rising edge to DOUT high-impedance | Output falling | VA = 3 V | 1.7 | 20 | ns | |
| VA = 5 V | 1.2 | 20 | |||||
| Output rising | VA = 3 V | 1 | 20 | ||||
| VA = 5 V | 1 | 20 | |||||
(1) Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).
(2) Clock may be either high or low when CS is asserted as long as setup and hold times tCSU and tCLH are strictly observed.
Figure 1. Operational Timing Diagram
Figure 2. Timing Test Circuit
Figure 3. Serial Timing Diagram
Figure 4. SCLK and CS Timing Parameters
7.7 Typical Characteristics
TA = 25°C, fSAMPLE = 50 ksps to 200 ksps, fSCLK = 0.8 MHz to 3.2 MHz, and fIN = 39.9 kHz (unless otherwise noted)
Figure 5. DNL – VA = 3 V
Figure 7. DNL – VA = 5 V
Figure 9. DNL vs Supply
Figure 11. DNL vs Clock Frequency
Figure 13. DNL vs Clock Duty Cycle
Figure 15. DNL vs Temperature
Figure 17. SNR vs Supply
Figure 19. SNR vs Clock Frequency
Figure 21. SNR vs Clock Duty Cycle
Figure 23. SNR vs Input Frequency
Figure 25. SNR vs Temperature
Figure 27. SFDR vs Supply
Figure 29. SFDR vs Clock Frequency
Figure 31. SFDR vs Clock Duty Cycle
Figure 33. SFDR vs Input Frequency
Figure 35. SFDR vs Temperature
Figure 37. ENOB vs Supply
Figure 39. ENOB vs Clock Duty Cycle
Figure 41. ENOB vs Temperature
Figure 43. Spectral Response: 5 V, 200 ksps
Figure 6. INL – VA = 3 V
Figure 8. INL – VA = 5 V
Figure 10. INL vs Supply
Figure 12. INL vs Clock Frequency
Figure 14. INL vs Clock Duty Cycle
Figure 16. INL vs Temperature
Figure 18. THD vs Supply
Figure 20. THD vs Clock Frequency
Figure 22. THD vs Clock Duty Cycle
Figure 24. THD vs Input Frequency
Figure 26. THD vs Temperature
Figure 28. SINAD vs Supply
Figure 30. SINAD vs Clock Frequency
Figure 32. SINAD vs Clock Duty Cycle
Figure 34. SINAD vs Input Frequency
Figure 36. SINAD vs Temperature
Figure 38. ENOB vs Clock Frequency
Figure 40. ENOB vs Input Frequency
Figure 42. Spectral Response: 3 V, 200 ksps
Figure 44. Power Consumption vs Throughput