ZHCSN42A August 2021 – May 2022 ADC08DJ5200RF
PRODUCTION DATA
| MIN | NOM | MAX | UNIT | |||
|---|---|---|---|---|---|---|
| DEVICE (SAMPLING) CLOCK (CLK+, CLK–) | ||||||
| fCLK | Input clock frequency (CLK±), both single-channel and dual-channel modes(1) | 800 | 5200 | MHz | ||
| tCLK | Input clock period (CLK±), both single-channel and dual-channel modes(1) | 192 | 1250 | ps | ||
| SYSREF (SYSREF+, SYSREF–) | ||||||
| tINV(SYSREF) | Width of invalid SYSREF capture region of CLK± period, indicating setup or hold time violation, as measured by SYSREF_POS status register, SYSREF_ZOOM = 1(2) | 48 | ps | |||
| tINV(TEMP) | Drift of invalid SYSREF capture region over temperature, positive number indicates a shift toward MSB of SYSREF_POS register, SYSREF_ZOOM = 1 | 0.02 | ps/°C | |||
| tINV(VA11) | Drift of invalid SYSREF capture region over VA11 supply voltage, positive number indicates a shift toward MSB of SYSREF_POS register, SYSREF_ZOOM = 1 | -0.03 | ps/mV | |||
| tSTEP(SP) | Delay of SYSREF_POS LSB(3) | SYSREF_ZOOM = 0 | 39 | ps | ||
| SYSREF_ZOOM = 1 | 24 | |||||
| t(PH_SYS) | Minimum SYSREF± assertion duration with SYSREF Windowing after SYSREF± rising edge event | 5*TCLK +4.5 |
ns | |||
| t(PL_SYS) | Minimum SYSREF± de-assertion duration with SYSREF Windowing after SYSREF± falling edge event | 5*TCLK +4.5 |
ns | |||
| JESD204B SYNC TIMING (SYNCSE OR TMSTP±) | ||||||
| t(SYNCSE) | SYNCSE minimum assertion time to trigger link resynchronization | 4 | Frames | |||
| SERIAL PROGRAMMING INTERFACE (SCLK, SDI, SCS) | ||||||
| fCLK(SCLK) | Serial clock frequency | 15.625 | MHz | |||
| t(PH) | Serial clock high value pulse duration | 32 | ns | |||
| t(PL) | Serial clock low value pulse duration | 32 | ns | |||
| tSU(SCS) | Setup time from SCS to rising edge of SCLK | 30 | ns | |||
| tH(SCS) | Hold time from rising edge of SCLK to SCS | 30 | ns | |||
| tSU(SDI) | Setup time from SDI to rising edge of SCLK | 25 | ns | |||
| tH(SDI) | Hold time from rising edge of SCLK to SDI | 3 | ns | |||