ZHCSON8A July 2021 – October 2024 ADC09DJ800-Q1 , ADC09QJ800-Q1 , ADC09SJ800-Q1
PRODUCTION DATA
Table 6-55 lists the parameters that can be trimmed and the associated registers.
| TRIM PARAMETER | TRIM REGISTER | NOTES |
|---|---|---|
| Band-gap reference | BG_TRIM | Measurement on BG output pin. |
| Input termination resistance | RTRIM_x, where x = A for INA±, B for INB±, etc. | The device must be powered on with a clock applied. The registers corresponding to the unused inputs for dual and single channel devices the have no affect. |
| Input offset voltage | OFSxy, where x = ADC core (0, 1, 2, 3, 4, or 5) and y = A for INA±, B for INB±, etc. or omitted (for ADC cores 0, 1, 4 and 5) | A different trim value is allowed for each ADC core (0, 1, 2, 3, 4 or 5) to allow more consistent offset performance in background calibration mode. Use CAL_OS with CAL_BG = 1 to get the trim values from these registers. The registers corresponding to the unused inputs for dual and single channel devices the have no affect. |
| Analog input gain | GAINxy, where x = ADC core (0, 1, 2, 3, 4, or 5) and y = A for INA±, B for INB±, etc. or omitted (for ADC cores 0, 1, 4 and 5) | Use this trim to match the gain for each ADC core. These registers are not affected by the calibration process. The registers corresponding to the unused inputs for dual and single channel devices the have no affect. |
| Full-scale input voltage | FS_RANGE | Full-scale input voltage adjustment that applies to all inputs. Use GAINxy to match the gain for each input. |