ZHCSOS8A October 2021 – October 2024 ADC09DJ1300 , ADC09QJ1300 , ADC09SJ1300
PRODUCTION DATA
The PD input pin allows the device devices to be entirely powered down. Power-down can also be controlled by MODE. The serial data output drivers are disabled when PD is high. When the device returns to normal operation, the JESD204 link must be re-established and the ADC pipelines contain meaningless information so the system must wait a sufficient time for the data to be flushed. The register configuration and calibration data is maintained during power down. A calibration cycle (foreground or background calibration) may be needed to return to optimal performance if the temperature changes drastically during the duration of power down. Pairs of channels can also be powered down using the CH_EN register. Do not use CH_EN to power down all four channels, use MODE or the PD pin instead.