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ZHCSOS8A October 2021 – October 2024 ADC09DJ1300 , ADC09QJ1300 , ADC09SJ1300

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AAV|144
- MPBGAM2C

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5.8 Timing Requirements

			MIN	NOM	MAX	UNIT
ADC SAMPLING CLOCK
f_S	ADC core sampling clock frequency	High Performance Mode	500⁽¹⁾		1300⁽¹⁾	MHz
	ADC core sampling clock frequency	Low Power Mode	500⁽¹⁾		1000⁽¹⁾	MHz
	ADC core minimum sampling clock frequency	Low Power Mode		500⁽¹⁾		MHz
t_S	ADC core sampling clock period	High Performance Mode	770⁽¹⁾		2000⁽¹⁾	ps
	ADC core sampling clock period	Low Power Mode	1000⁽¹⁾		2000⁽¹⁾	ps
	ADC core maximum sampling clock period	Low Power Mode		2000⁽¹⁾		ps
CLOCK INPUTS (CLK+, CLK–, SE_CLK)
f_CLK	CLK± input frequency	PLL Disabled	500		1300	MHz
f_CLK	CLK± input frequency	PLL Enabled, PLLREF_SE = 0	50		500	MHz
f_{SE_CLK}	SE_CLK input frequency	PLL Enabled, PLLREF_SE = 1	50		500	MHz
DC_(CLKMIN)	Minimum Input clock duty cycle (CLK± and SE_CLK)	Input clock duty cycle (CLK± and SE_CLK)		40%
DC_(CLKMAX)	Maximum Input clock duty cycle (CLK± and SE_CLK)	Input clock duty cycle (CLK± and SE_CLK)		60%
PHASE-LOCKED LOOP (PLL) AND VOLTAGE-CONTROLLED OSCILLATOR (VCO)
f_PLLPFD	PLL phase-frequency detector (PFD) frequency	PLL Enabled	50		500	MHz
f_VCO	Closed-loop voltage-controlled oscillator (VCO) frequency	PLL Enabled	7200		8200	MHz
SYSREF (SYSREF+, SYSREF–)
t_INV(SYSREF)	Width of invalid SYSREF capture region of CLK± period, indicating setup or hold time violation, as measured by SYSREF_POS status register⁽²⁾			250		ps
t_INV(TEMP)	Drift of invalid SYSREF capture region over temperature, positive number indicates a shift toward MSB of SYSREF_POS register			0.033		ps/°C
t_INV(VA11)	Drift of invalid SYSREF capture region over VA11 supply voltage, positive number indicates a shift toward MSB of SYSREF_POS register			-0.127		ps/mV
t_STEP(SP)	Delay of SYSREF_POS LSB	SYSREF_ZOOM = 0		125		ps
t_STEP(SP)	Delay of SYSREF_POS LSB	SYSREF_ZOOM = 1		69		ps
DC_(SYSREF)	SYSREF duty cycle (asserted) when using a periodic SYSREF signal			50%	55%
t_{(PH_SYS)}	Minimum SYSREF± assertion duration after SYSREF± rising edge event			4		ns
JESD204C SYNC TIMING (SYNCSE)
SERIAL PROGRAMMING INTERFACE (SCLK, SDI, SCS)
f_CLK(SCLK)	Serial clock frequency		0		15.625	MHz
t_(PH)	Serial clock high value pulse duration			32		ns
t_(PL)	Serial clock low value pulse duration			32		ns
t_SU(SCS)	Setup time from SCS to rising edge of SCLK			25		ns
t_H(SCS)	Hold time from rising edge of SCLK to SCS			3		ns
t_SU(SDI)	Setup time from SDI to rising edge of SCLK			25		ns
t_H(SDI)	Hold time from rising edge of SCLK to SDI			3		ns

(1) Unless functionally limited to a smaller range in the tables Operating Modes for Quad Channel Device through Operating Modes for Single Channel Device based on programmed JMODE.

(2) Use SYSREF_POS to select an optimal SYSREF_SEL value for the SYSREF capture, see the section SYSREF Windowing for more information on SYSREF windowing. The invalid region, specified by t_INV(SYSREF), indicates the portion of the CLK± period(t_CLK), as measured by SYSREF_SEL, that may result in a setup and hold violation. Verify that the timing skew between SYSREF± and CLK± over system operating conditions from the nominal conditions (that used to find optimal SYSREF_SEL) does not result in the invalid region occurring at the selected SYSREF_SEL position in SYSREF_POS, otherwise a temperature dependent SYSREF_SEL selection may be needed to track the skew between CLK± and SYSREF±.