ZHCSP08A October   2021  – October 2024 ADC09DJ800 , ADC09QJ800 , ADC09SJ800

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: DC Specifications
    6. 5.6  Electrical Characteristics: Power Consumption
    7. 5.7  Electrical Characteristics: AC Specifications
    8. 5.8  Timing Requirements
    9. 5.9  Switching Characteristics
    10. 5.10 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Device Comparison
      2. 6.3.2 Analog Input
        1. 6.3.2.1 Analog Input Protection
        2. 6.3.2.2 Full-Scale Voltage (VFS) Adjustment
        3. 6.3.2.3 Analog Input Offset Adjust
        4. 6.3.2.4 ADC Core
          1. 6.3.2.4.1 ADC Theory of Operation
          2. 6.3.2.4.2 ADC Core Calibration
          3. 6.3.2.4.3 Analog Reference Voltage
          4. 6.3.2.4.4 ADC Over-range Detection
          5. 6.3.2.4.5 Code Error Rate (CER)
      3. 6.3.3 Temperature Monitoring Diode
      4. 6.3.4 Timestamp
      5. 6.3.5 Clocking
        1. 6.3.5.1 Converter PLL (C-PLL) for Sampling Clock Generation
        2. 6.3.5.2 LVDS Clock Outputs (PLLREFO±, TRIGOUT±)
        3. 6.3.5.3 Optional CMOS Clock Outputs (ORC, ORD)
        4. 6.3.5.4 SYSREF for JESD204C Subclass-1 Deterministic Latency
          1. 6.3.5.4.1 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          2. 6.3.5.4.2 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
      6. 6.3.6 JESD204C Interface
        1. 6.3.6.1  Transport Layer
        2. 6.3.6.2  Scrambler
        3. 6.3.6.3  Link Layer
        4. 6.3.6.4  8B/10B Link Layer
          1. 6.3.6.4.1 Data Encoding (8B/10B)
          2. 6.3.6.4.2 Multiframes and the Local Multiframe Clock (LMFC)
          3. 6.3.6.4.3 Code Group Synchronization (CGS)
          4. 6.3.6.4.4 Initial Lane Alignment Sequence (ILAS)
          5. 6.3.6.4.5 Frame and Multiframe Monitoring
        5. 6.3.6.5  64B/66B Link Layer
          1. 6.3.6.5.1 64B/66B Encoding
          2. 6.3.6.5.2 Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)
            1. 6.3.6.5.2.1 Block, Multiblock and Extended Multiblock Alignment using Sync Header
              1. 6.3.6.5.2.1.1 Cyclic Redundancy Check (CRC) Mode
              2. 6.3.6.5.2.1.2 Forward Error Correction (FEC) Mode
          3. 6.3.6.5.3 Initial Lane Alignment
          4. 6.3.6.5.4 Block, Multiblock and Extended Multiblock Alignment Monitoring
        6. 6.3.6.6  Physical Layer
          1. 6.3.6.6.1 SerDes Pre-Emphasis
        7. 6.3.6.7  JESD204C Enable
        8. 6.3.6.8  Multi-Device Synchronization and Deterministic Latency
        9. 6.3.6.9  Operation in Subclass 0 Systems
        10. 6.3.6.10 Alarm Monitoring
          1. 6.3.6.10.1 Clock Upset Detection
          2. 6.3.6.10.2 FIFO Upset Detection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Low Power Mode and High Performance Mode
      2. 6.4.2 JESD204C Modes
        1. 6.4.2.1 JESD204C Transport Layer Data Formats
        2. 6.4.2.2 64B/66B Sync Header Stream Configuration
        3. 6.4.2.3 Redundant Data Mode (Alternate Lanes)
      3. 6.4.3 Power-Down Modes
      4. 6.4.4 Test Modes
        1. 6.4.4.1 Serializer Test-Mode Details
        2. 6.4.4.2 PRBS Test Modes
        3. 6.4.4.3 Clock Pattern Mode
        4. 6.4.4.4 Ramp Test Mode
        5. 6.4.4.5 Short and Long Transport Test Mode
          1. 6.4.4.5.1 Short Transport Test Pattern
        6. 6.4.4.6 D21.5 Test Mode
        7. 6.4.4.7 K28.5 Test Mode
        8. 6.4.4.8 Repeated ILA Test Mode
        9. 6.4.4.9 Modified RPAT Test Mode
      5. 6.4.5 Calibration Modes and Trimming
        1. 6.4.5.1 Foreground Calibration Mode
        2. 6.4.5.2 Background Calibration Mode
        3. 6.4.5.3 Low-Power Background Calibration (LPBG) Mode
      6. 6.4.6 Offset Calibration
      7. 6.4.7 Trimming
    5. 6.5 Programming
      1. 6.5.1 Using the Serial Interface
      2. 6.5.2 SCS
      3. 6.5.3 SCLK
      4. 6.5.4 SDI
      5. 6.5.5 SDO
      6. 6.5.6 Streaming Mode
      7. 6.5.7 SPI_Register_Map Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Light Detection and Ranging (LiDAR) Digitizer
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Analog Front-End Requirements
          2. 7.2.1.2.2 Calculating Clock and SerDes Frequencies
        3. 7.2.1.3 Application Curves
    3. 7.3 Initialization Set Up
    4. 7.4 Power Supply Recommendations
      1. 7.4.1 Power Sequencing
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
    2. 8.2 接收文档更新通知
    3. 8.3 支持资源
    4. 8.4 Trademarks
    5. 8.5 静电放电警告
    6. 8.6 术语表
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.4.2.1 JESD204C Transport Layer Data Formats

The ADC core output samples are formatted in a specific fashion for each JMODE setting based on the transport layer settings for that JMODE. The following tables show the specific mapping formats for a single frame for each JMODE. The symbol definitions used in the JMODE tables is provided in Table 6-20. In all mappings the tail bits (T) are 0 (zero). All samples are formatted as MSB first, LSB last.

Table 6-20 JMODE Table Symbol Definitions
NOTATIONDESCRIPTION
AnSample n from channel A
BnSample n from channel B
CnSample n from channel C
DnSample n from channel D
TTail bits, always set to 0
Table 6-21 JMODE 0 (9-bit, 8/4/2 lanes, 8B/10B)
OCTET01234567
NIBBLE0123456789101112131415
D0A0[8:0],000A2[8:0],000A4[8:0],000A6[8:0],000A8[8:0],000T
D1A1[8:0],000A3[8:0],000A5[8:0],000A7[8:0],000A9[8:0],000T
D2B0[8:0],000B2[8:0],000B4[8:0],000B6[8:0],000B8[8:0],000T
D3B1[8:0],000B3[8:0],000B5[8:0],000B7[8:0],000B9[8:0],000T
D4 (Quad only)C0[8:0],000C2[8:0],000C4[8:0],000C6[8:0],000C8[8:0],000T
D5 (Quad only)C1[8:0],000C3[8:0],000C5[8:0],000C7[8:0],000C9[8:0],000T
D6 (Quad only)D0[8:0],000D2[8:0],000D4,000D6[8:0],000D8[8:0],000T
D7 (Quad only)D1[8:0],000D3[8:0],000D5[8:0],000D7[8:0],000D9[8:0],000T
Table 6-22 JMODE 1 (9-bit, 6/3/2 lanes, 8B/10B)
OCTET01
NIBBLE0123
D0A0[8:0], 000A1[8:5]
D1A1[4:0], 000

Dual or Quad: B0[8:1]

Single: 0x00

D2 (Quad or Dual only)B0[0], 000B1[8:0], 000
D3 (Quad only)C0[8:0], 000C1[8:5]
D4 (Quad only)C1[4:0], 000D0[8:1]
D5 (Quad only)D0[0], 000D1[8:0], 000
Table 6-23 JMODE 2 (8-bit, 4/2/1 lanes, 8B/10B)
OCTET0
NIBBLE01
D0A0
D1 (Dual or Quad only)B0
D2 (Quad only)C0
D3 (Quad only)D0
Table 6-24 JMODE 3 (9-bit, 4/2/1 lanes, 8B/10B)
OCTET01234
NIBBLE0123456789
D0A0[8:0], 0A1[8:0], 0A2[8:0], 0A3[8:0], 0
D1 (Dual or Quad only)B0[8:0], 0B1[8:0], 0B2[8:0], 0B3[8:0], 0
D2 (Quad only)C0[8:0], 0C1[8:0], 0C2[8:0], 0C3[8:0], 0
D3 (Quad only)D0[8:0], 0D1[8:0], 0D2[8:0], 0D3[8:0], 0
Table 6-25 JMODE 4 (9-bit, 3/2/1lanes, 64B/66B)
OCTET01
NIBBLE0123
D0A0[8:0], 000Quad or Dual: B0[8:5]
Single: 0x0
D1 (Dual or Quad only)B0[4:0], 000Quad: C0[9:1]
Dual: 0x00
D2 (Quad only)C0[0], 000D0[8:0], 000
Table 6-26 JMODE 5 (8-bit, 2/1/1 lanes, 64B/66B)
OCTET01
NIBBLE0123
D0A0Quad or Dual: B0
Single: 0x00
D1 (Quad Only)C0D0
Table 6-27 JMODE 6 (9-bit, 6/3/2 lanes, 64B/66B)
OCTET01
NIBBLE0123
D0A0[8:0], 000A1[8:5]
D1A1[4:0], 000Dual or Quad: B0[8:1]
Single: 0x00
D2 (Dual or Quad only)B0[0], 000B1[8:0], 000
D3 (Quad only)C0[8:0], 000C1[8:5]
D4 (Quad only)C1[4:0], 000D0[8:1]
D5 (Quad only)D0[0], 000D1[8:0], 000
Table 6-28 JMODE 7 (8-bit, 4/2/1 lanes, 64B/66B)
OCTET0
NIBBLE01
D0A0
D1 (Dual or Quad only)B0
D2 (Quad only)C0
D3 (Quad only)D0
Table 6-29 JMODE 8 (12-bit, 4/2/1 lanes, 64B/66B)
OCTET012
NIBBLE012345
D0A0[8:0], 000A1[8:0], 000
D1 (Dual or Quad only)B0[8:0], 000B1[8:0], 000
D2 (Quad only)C0[8:0], 000C1[8:0], 000
D3 (Quad only)D0[8:0], 000D1[8:0], 000
Table 6-30 JMODE 9 (8-bit, 8/4/2lanes, 8B/10B)
OCTET0
NIBBLE01
D0A0
D1A1
D2 (Dual or Quad only)B0
D3 (Dual or Quad only)B1
D4 (Quad only)C0
D5 (Quad only)C1
D6 (Quad only)D0
D7 (Quad only)D1
Table 6-31 JMODE 10 (9-bit, 8/4/2 lanes, 8B/10B)
OCTET01234
NIBBLE0123456789
D0A0[8:0], 0A2[8:0], 0A4[8:0], 0A6[8:0], 0
D1A1[8:0], 0A3[8:0], 0A5[8:0], 0A7[8:0], 0
D2 (Dual or Quad only)B0[8:0], 0B2[8:0], 0B4[8:0], 0B6[8:0], 0
D3 (Dual or Quad only)B1[8:0], 0B3[8:0], 0B5[8:0], 0B7[8:0], 0
D4 (Quad only)C0[8:0], 0C2[8:0], 0C4[8:0], 0C6[8:0], 0
D5 (Quad only)C1[8:0], 0C3[8:0], 0C5[8:0], 0C7[8:0], 0
D6 (Quad only)D0[8:0], 0D2[8:0], 0D4[8:0], 0D6[8:0], 0
D7 (Quad only)D1[8:0], 0D3[8:0], 0D5[8:0], 0D7[8:0], 0
Table 6-32 JMODE 11 (9-bit, Dual/Single channel only, 8/4 lanes, 8B/10B)
OCTET01234567
NIBBLE0123456789101112131415
D0A0[8:0], 000A4[8:0], 000A8[8:0], 000A12[8:0], 000A16[8:0], 000T
D1A1[8:0], 000A5[8:0], 000A9[8:0], 000A13[8:0], 000A17[8:0], 000T
D2A2[8:0], 000A6[8:0], 000A10[8:0], 000A14[8:0], 000A18[8:0], 000T
D3A3[8:0], 000A7[8:0], 000A11[8:0], 000A15[8:0], 000A19[8:0], 000T
D4 (Dual only)B0[8:0], 000B4[8:0], 000B8[8:0], 000B12[8:0], 000B16[8:0], 000T
D5 (Dual only)B1[8:0], 000B5[8:0], 000B9[8:0], 000B13[8:0], 000B17[8:0], 000T
D6 (Dual only)B2[8:0], 000B6[8:0], 000B10[8:0], 000B14[8:0], 000B18[8:0], 000T
D7 (Dual only)B3[8:0], 000B7[8:0], 000B11[8:0], 000B15[8:0], 000B19[8:0], 000T
Table 6-33 JMODE 12 (8-bit, Dual/Single channel only, 8/4 lanes, 64B/66B)
OCTET0
NIBBLE01
D0A0
D1A1
D2A2
D3A3
D4 (Dual only)B0
D5 (Dual only)B1
D6 (Dual only)B2
D7 (Dual only)B3
Table 6-34 JMODE 13 (9-bit, Dual/Single channel only, 8/4lanes, 8B/10B)
OCTET01234
NIBBLE0123456789
D0A0[8:0], 0A4[8:0], 0A8[8:0], 0A12[8:0], 0
D1A1[8:0], 0A5[8:0], 0A9[8:0], 0A13[8:0], 0
D2A2[8:0], 0A6[8:0], 0A10[8:0], 0A14[8:0], 0
D3A3[8:0], 0A7[8:0], 0A11[8:0], 0A15[8:0], 0
D4 (Dual only)B0[8:0], 0B4[8:0], 0B8[8:0], 0B12[8:0], 0
D5 (Dual only)B1[8:0], 0B5[8:0], 0B9[8:0], 0B13[8:0], 0
D6 (Dual only)B2[8:0], 0B6[8:0], 0B10[8:0], 0B14[8:0], 0
D7 (Dual only)B3[8:0], 0B7[8:0], 0B11[8:0], 0B15[8:0], 0
Table 6-35 JMODE 14 (9-bit, 8/4/2 lanes, 64B/66B)
OCTET012
NIBBLE012345
D0A0[8:0], 000A2[8:0], 000
D1A1[8:0], 000A3[8:0], 000
D2 (Dual or Quad only)B0[8:0], 000B2[8:0], 000
D3 (Dual or Quad only)B1[8:0], 000B3[8:0], 000
D4 (Quad only)C0[8:0], 000C2[8:0], 000
D5 (Quad only)C1[8:0], 000C3[8:0], 000
D6 (Quad only)D0[8:0], 000D2[8:0], 000
D7 (Quad only)D1[8:0], 000D3[8:0], 000
Table 6-36 JMODE 15 (9-bit, Dual/Single channel only, 8/4 lanes, 64B/66B)
OCTET012
NIBBLE012345
D0A0[8:0], 000A4[8:0], 000
D1A1[8:0], 000A5[8:0], 000
D2A2[8:0], 000A6[8:0], 000
D3A3[8:0], 000A7[8:0], 000
D4 (Dual only)B0[8:0], 000B4[8:0], 000
D5 (Dual only)B1[8:0], 000B5[8:0], 000
D6 (Dual only)B2[8:0], 000B6[8:0], 000
D7 (Dual only)B3[8:0], 000B7[8:0], 000
千亿体育app官网登录(中国)官方网站IOS/安卓通用版/手机APP | 米乐app下载官网（中国）|ios|Android/通用版APP最新版 | 米乐|米乐·M6（中国大陆）官方网站 | 千亿体育登陆地址 | 华体会体育（中国）HTH·官方网站 | 千赢qy国际_全站最新版千赢qy国际V6.2.14安卓/IOS下载 | 18新利网v1.2.5|中国官方网站 | bob电竞真人（中国官网）安卓/ios苹果/电脑版【1.97.95版下载】 | 千亿体育app官方下载(中国)官方网站IOS/安卓/手机APP下载安装 |