SNAS466G February   2009  – December 2016 ADC10D1000QML-SP

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Converter Electrical Characteristics: Static Converter Characteristics
    6. 6.6  Converter Electrical Characteristics: Dynamic Converter Characteristics
    7. 6.7  Converter Electrical Characteristics: Analog Input/Output and Reference Characteristics
    8. 6.8  Converter Electrical Characteristics: Channel-to-Channel Characteristics
    9. 6.9  Converter Electrical Characteristics: LVDS CLK Input Characteristics
    10. 6.10 Electrical Characteristics: AutoSync Feature
    11. 6.11 Converter Electrical Characteristics: Digital Control and Output Pin Characteristics
    12. 6.12 Converter Electrical Characteristics: Power Supply Characteristics (1:2 Demux Mode)
    13. 6.13 Converter Electrical Characteristics: AC Electrical Characteristics
    14. 6.14 Timing Requirements: Serial Port Interface
    15. 6.15 Timing Requirements: Calibration
    16. 6.16 Quality Conformance Inspection
    17. 6.17 Timing Diagrams
    18. 6.18 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Features
        1. 7.3.1.1 Input Control and Adjust
          1. 7.3.1.1.1 AC- and DC-Coupled Modes
          2. 7.3.1.1.2 Input Full-Scale Range Adjust
          3. 7.3.1.1.3 Input Offset Adjust
          4. 7.3.1.1.4 DES/Non-DES Mode
          5. 7.3.1.1.5 Sampling Clock Phase Adjust
          6. 7.3.1.1.6 LC Filter-On Input Clock
          7. 7.3.1.1.7 VCMO Adjust
        2. 7.3.1.2 Output Control and Adjust
          1. 7.3.1.2.1 DDR Clock Phase
          2. 7.3.1.2.2 LVDS Output Differential Voltage
          3. 7.3.1.2.3 LVDS Output Common-Mode Voltage
          4. 7.3.1.2.4 Output Formatting
          5. 7.3.1.2.5 Demux/Non-Demux Mode
          6. 7.3.1.2.6 Test Pattern Mode
        3. 7.3.1.3 Calibration Feature
          1. 7.3.1.3.1 Calibration Pins
          2. 7.3.1.3.2 How to Initiate a Calibration Event
          3. 7.3.1.3.3 On-Command Calibration
          4. 7.3.1.3.4 Calibration Adjust
          5. 7.3.1.3.5 Calibration and Power Down
          6. 7.3.1.3.6 Read/Write Calibration Settings
        4. 7.3.1.4 Power Down
      2. 7.3.2 Power-On Reset
    4. 7.4 Device Functional Modes
      1. 7.4.1 Control Modes
        1. 7.4.1.1 Non-Extended Control Mode
          1. 7.4.1.1.1 Non-Demultiplexed Mode Pin (NDM)
          2. 7.4.1.1.2 Dual Data-Rate Phase Pin (DDRPh)
          3. 7.4.1.1.3 Calibration Pin (CAL)
          4. 7.4.1.1.4 Power-Down I-Channel Pin (PDI)
          5. 7.4.1.1.5 Power-Down Q-Channel Pin (PDQ)
          6. 7.4.1.1.6 Test Pattern Mode Pin (TPM)
          7. 7.4.1.1.7 Full-Scale Input Range Pin (FSR)
          8. 7.4.1.1.8 AC-DC-Coupled Mode Pin (VCMO)
          9. 7.4.1.1.9 LVDS Output Common-Mode Pin (VBG)
      2. 7.4.2 Extended Control Mode
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
    6. 7.6 Register Maps
      1. 7.6.1 Register Definitions
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Analog Inputs
        1. 8.1.1.1 Acquiring the Input
        2. 8.1.1.2 Terminating Unused Analog Inputs
        3. 8.1.1.3 Reference Voltage and FSR
        4. 8.1.1.4 Out-of-Range Indication
        5. 8.1.1.5 AC-Coupled Input Signals
        6. 8.1.1.6 DC-Coupled Input Signals
        7. 8.1.1.7 Single-Ended Input Signals
      2. 8.1.2 Clock Inputs
        1. 8.1.2.1 CLK Coupling
        2. 8.1.2.2 CLK Frequency
        3. 8.1.2.3 CLK Level
        4. 8.1.2.4 CLK Duty Cycle
        5. 8.1.2.5 CLK Jitter
        6. 8.1.2.6 CLK Layout
      3. 8.1.3 The LVDS Outputs
        1. 8.1.3.1 Common-Mode and Differential Voltage
        2. 8.1.3.2 Output Data Rate
      4. 8.1.4 Synchronizing Multiple ADC10D1000S in a System
        1. 8.1.4.1 AutoSync Feature
        2. 8.1.4.2 DCLK Reset Feature
  9. Power Supply Recommendations
    1. 9.1 Power Planes
      1. 9.1.1 Bypass Capacitors
        1. 9.1.1.1 Ground Plane
        2. 9.1.1.2 Power Supply Example
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Mounting Recommendation
    2. 10.2 Layout Example
    3. 10.3 Thermal Management
    4. 10.4 Temperature Sensor Diode
    5. 10.5 Radiation Environments
      1. 10.5.1 Total Ionizing Dose
      2. 10.5.2 Single Event Latch-Up and Functional Interrupt
      3. 10.5.3 Single Event Upset
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
        1. 11.1.2.1 Specification Definitions
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Engineering Samples

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Device and Documentation Support

Device Support

Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

Device Nomenclature

Specification Definitions

APERTURE (SAMPLING) DELAY is the amount of delay, measured from the sampling edge of the CLK input, after which the signal present at the input pin is sampled inside the device.

APERTURE JITTER (tAJ) is the variation in aperture delay from sample-to-sample. Aperture jitter can be effectively considered as noise at the input.

CODE ERROR RATE (C.E.R.) is the probability of error and is defined as the probable number of word errors on the ADC output per unit of time divided by the number of words seen in that amount of time. A CER of 10-18 corresponds to a statistical error in one word about every four (4) years.

CLOCK DUTY CYCLE is the ratio of the time that the clock waveform is at a logic high to the total time of one clock period.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB. It is measured at sample rate = 500 MSPS with a 1-MHz input sine wave.

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise and Distortion Ratio, or SINAD. ENOB is defined as (SINAD − 1.76) / 6.02 and states that the converter is equivalent to a perfect ADC of this many (ENOB) number of bits.

FULL POWER BANDWIDTH (FPBW) is a measure of the frequency at which the reconstructed output fundamental drops to 3 dB below its low frequency value for a full-scale input.

GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated from Offset and Full-Scale Errors. The Positive Gain Error is the Offset Error minus the Positive Full-Scale Error. The Negative Gain Error is the Negative Full-Scale Error minus the Offset Error. The Gain Error is the Negative Full-Scale Error minus the Positive Full-Scale Error; it is also equal to the Positive Gain Error plus the Negative Gain Error.

INTEGRAL NON-LINEARITY (INL) is a measure of worst case deviation of the ADC transfer function from an ideal straight line drawn through the ADC transfer function. The deviation of any given code from this straight line is measured from the center of that code value step. The best fit method is used.

INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the power in the second and third order intermodulation products to the power in one of the original frequencies. IMD is usually expressed in dBFS.

LSB (LEAST SIGNIFICANT BIT) is the bit that has the smallest value or weight of all bits. This value is

Equation 2. VFS / 2N

where VFS is the differential full-scale amplitude VIN as set by the FSR input and "N" is the ADC resolution in bits, which is 10 for the ADC10D1000.

LOW VOLTAGE DIFFERENTIAL SIGNALING (LVDS) DIFFERENTIAL OUTPUT VOLTAGE (VID and VOD) is two times the absolute value of the difference between the VD+ and VD– signals; each measured with respect to Ground.

ADC10D1000QML-SP 30071846.gif Figure 53. LVDS Output Signal Levels

LVDS OUTPUT OFFSET VOLTAGE (VOS) is the midpoint between the D+ and D– pins output voltage with respect to ground; that is, [(VD+) +( VD-)]/2. See Figure 53.

MISSING CODES are those output codes that are skipped and will never appear at the ADC outputs. These codes cannot be reached with any input value.

MSB (MOST SIGNIFICANT BIT) is the bit that has the largest value or weight. Its value is one half of full scale.

NEGATIVE FULL-SCALE ERROR (NFSE) is a measure of how far the first code transition is from the ideal 1/2 LSB above a differential −VIN/2 with the FSR pin low. For the ADC10D1000 the reference voltage is assumed to be ideal, so this error is a combination of full-scale error and reference voltage error.

NOISE POWER RATIO (NPR) is the ratio of the sum of the power inside the notched bins to the sum of the power in an equal number of bins outside the notch, expressed in dB.

OFFSET ERROR (VOFF) is a measure of how far the mid-scale point is from the ideal zero voltage differential input. Offset Error = Actual Input causing average of 8k samples to result in an average code of 511.5.

OUTPUT DELAY (tOD) is the time delay (in addition to Pipeline Delay) after the falling edge of CLK+ before the data update is present at the output pins.

OVER-RANGE RECOVERY TIME is the time required after the differential input voltages goes from ±1.2 V to 0 V for the converter to recover and make a conversion with its rated accuracy.

PIPELINE DELAY (LATENCY) is the number of input clock cycles between initiation of conversion and when that data is presented to the output driver stage. New data is available at every clock cycle, but the data lags the conversion by the Pipeline Delay plus the tOD.

POSITIVE FULL-SCALE ERROR (PFSE) is a measure of how far the last code transition is from the ideal 1-1/2 LSB below a differential +VIN/2. For the ADC10D1000 the reference voltage is assumed to be ideal, so this error is a combination of full-scale error and reference voltage error.

POWER SUPPLY REJECTION RATIO (PSRR) is the ratio of the change in full-scale error that results from a power supply voltage change from 1.8 V to 2 V. PSRR is expressed in dB.

SIGNAL-TO-NOISE RATIO (SNR) is the ratio, expressed in dB, of the RMS value of the input signal at the output to the RMS value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or DC.

SIGNAL-TO-NOISE PLUS DISTORTION (S/(N+D) or SINAD) is the ratio, expressed in dB, of the RMS value of the input signal at the output to the RMS value of all of the other spectral components below half the input clock frequency, including harmonics but excluding DC.

SPURIOUS-FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the RMS values of the input signal at the output and the peak spurious signal, where a spurious signal is any signal present in the output spectrum that is not present at the input, excluding DC.

TOTAL HARMONIC DISTORTION (THD) is the ratio expressed in dB, of the RMS total of the first nine harmonic levels at the output to the level of the fundamental at the output. THD is calculated as

Equation 3. ADC10D1000QML-SP 30071805.gif

where Af1 is the RMS power of the fundamental (output) frequency and Af2 through Af10 are the RMS power of the first 9 harmonic frequencies in the output spectrum.

– Second Harmonic Distortion (2nd Harm) is the difference, expressed in dB, between the RMS power in the input frequency seen at the output and the power in its 2nd harmonic level at the output.

– Third Harmonic Distortion (3rd Harm) is the difference expressed in dB between the RMS power in the input frequency seen at the output and the power in its 3rd harmonic level at the output.

Related Links

The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy.

Table 33. Related Links

PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY
ADC10D1000CCMLS Click here Click here Click here Click here Click here
ADC10D1000CVAL Click here Click here Click here Click here Click here

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Electrostatic Discharge Caution

esds-image

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

Glossary

SLYZ022TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.