| ANALOG FRONT-END AND CLOCK PINS |
| B1 |
VBG |
|
Bandgap voltage output or LVDS common-mode voltage select. This pin provides the bandgap output voltage and is capable of sourcing/ sinking 100 µA and driving a load of up to 80 pF. Alternately, this pin may be used to select the LVDS digital output common-mode voltage. If tied to logic-high, the higher LVDS common-mode voltage is selected. The lower value is the default. |
| C1/D2 |
Rtrim+
Rtrim– |
|
External reference and input termination trim resistor terminals. A 3.3-kΩ ±0.1% resistor must be connected between Rtrim+, Rtrim–. The Rtrim resistor is used to establish the calibrated 100-Ω input impedance of VinI+, Vinl–, VinQ+, VinQ– and CLK+, CLK-. These impedances may be fine-tuned by varying the value of the resistor by a corresponding percentage; however, the tuning range and performance is not ensured for such an alternate value. |
| C3/D3 |
Rext+
Rext– |
|
Connect a 3.3-kΩ ±0.1% resistor connected between Rext+, Rext–. The Rext resistor is used for setting internal temperature-independent bias currents; the value and precision of this resistor must not be compromised. |
| E2/F3 |
Tdiode+
Tdiode– |
|
Temperature sensor diode positive (anode) and negative (cathode) terminals. This set of pins is used for die temperature measurements. |
| C2 |
VCMO |
|
Common-mode voltage output or signal coupling select. If AC-coupled operation at the analog inputs is desired, this pin must be held at logic-low level. This pin is capable of sourcing and sinking up to 100 μA. For DC-coupled operation, VCMO, leave this pin floating or terminated into high-impedance. In DC-coupled mode, this pin provides an output voltage which is the optimal common-mode voltage for the input signal and should be used to set the common-mode voltage of the driving buffer. |
H1/J1
N1/M1 |
VinI+, Vinl–
VinQ+, VinQ– |
|
Differential signal I-channel and Q-channel inputs. In the non-dual edge sampling (non-DES) mode, each I-input and Q-input is sampled and converted by its respective channel with each positive transition of the CLK input. In non-extended control mode (non-ECM) and DES mode, both channels sample the I input. In extended control mode (ECM), the Q-channel input may optionally be selected for conversion in DES mode by the DEQ bit (Addr: 0h, Bit 6).
Each I-channel input and Q-channel input has an internal common mode bias that is disabled when DC-coupled mode is selected. Both inputs must be either AC- or DC-coupled. The coupling mode is selected by the VCMO pin.
In non-ECM, the full-scale range of these inputs is determined by the FSR pin; both I channel and Q-channels have the same full-scale input range. In ECM, the full-scale input range of the I- and Q-channel inputs may be independently set through the Control Register (Addr: 3h and Addr: Bh). The high and low full-scale input range setting in non-ECM corresponds to the mid and minimum full-scale input range in ECM.
The input offset may also be adjusted in ECM.
|
| U2/V1 |
CLK+
CLK– |
|
Differential converter sampling clock. In the non-DES mode, the analog inputs are sampled on the positive transitions of this clock signal. In the DES mode, the Q channel is sampled on both transitions of this clock. This clock must be AC-coupled. Additional features include an LC filter on the clock input. |
| V2/W1 |
DCLK_RST+
DCLK_RST– |
|
Differential DCLK reset. A positive pulse on this input is used to reset the DCLKI+, DCLKI– and DCLKQ+, DCLKQ– outputs of two or more ADC10D1000 devices in order to synchronize them with other ADC10D1000 devices in the system. DCLKI+, DCLKI– and DCLKQ+, DCLKQ– are always in phase with each other, unless one channel is powered down, and do not require a pulse from DCLK_RST+, DCLK_RST– to become synchronized. The pulse applied here must meet timing relationships with respect to the CLK+, CLK– inputs. This feature may still be used while the chip is in the AutoSync mode. |
| Y4/W5 |
RCLK+
RCLK– |
|
Reference clock input. When the AutoSync feature is active and the ADC10D1000 is in slave mode, the internal divided clocks are synchronized with respect to this input clock. The delay on this clock may be adjusted when synchronizing multiple ADCs. This feature is available in ECM via the Control Register (Addr: Eh). |
Y5/U6
V6/V7 |
RCOut1+, RCOut1–
RCOut2+, RCOut2– |
|
Reference clock output 1 and 2. These signals provide a reference clock at a rate of CLK/4, when enabled, independently of whether the ADC is in master or slave mode. They are used to drive the RCLK of another ADC10D1000, in order to enable automatic synchronization for multiple ADCs (AutoSync feature). The impedance of each trace from RCOut1+, RCOut1– and RCOut2+, RCOut2– to the RCLK+, RCLK– of another ADC10D1000 must be 100-Ω differential. Having two clock outputs allows the auto-synchronization to propagate as a binary tree. Use the DOC Bit (Addr: Eh, Bit 1) to enable/ disable this feature; the default is disabled. |
| CONTROL AND STATUS PINS |
| A3 |
SDO |
|
Serial data out. In ECM, serial data is shifted out of the device on this pin while SCS signal is asserted (logic-low). This output is in tri-state mode when SCS is de-asserted. |
| A4 |
TPM |
|
Test pattern mode. With this input at logic-high, the device continuously outputs a fixed, repetitive test pattern at the digital outputs. In the ECM, this input is ignored and the test pattern mode can only be activated through the TPM bit of the Control Register (Addr: 0h, Bit 12). |
| A5 |
NDM |
|
Non-demuxed mode. Setting this input to logic-high causes the digital output bus to be in the 1:1 Non-demuxed mode. Setting this input to logic-low causes the digital output bus to be in the 1:2 demuxed mode. This feature is pin-controlled only and remains active during ECM and non-ECM. |
| B3 |
ECE |
|
Extended control enable. Extended feature control through the SPI interface is enabled when this signal is asserted logic-low. In this case, most of the direct control pins have no effect. When this signal is de-asserted, that is, logic-high, the SPI interface is disabled and the direct control pins are enabled. |
| B4 |
SDI |
|
Serial data-in. In ECM, serial data is shifted into the device on this pin while the SCS signal is asserted (logic-low). |
| B5 |
CalRun |
|
Calibration running Indication. This output is logic-high while the calibration sequence is executing, and logic-low while the calibration sequence is not running. |
| C4 |
SCS |
|
Serial chip select. In ECM, when this signal is asserted logic-low, SCLK is used to clock in serial data that is present on the SDI input and to source serial data on the SDO output. When this signal is de-asserted, that is, logic-high, the SDI input is ignored and the SDO output is in tri-state mode. |
| C5 |
SCLK |
|
Serial clock. In ECM, serial data is shifted into and out of the device synchronously to this clock signal. This clock may be disabled and held logic-low, so long as timing specifications are not violated when the clock is enabled or disabled. |
| D6 |
CAL |
|
Calibration cycle initiate. The user can command the device to execute a self-calibration cycle by holding this input high a minimum of tCAL_H after having held it low a minimum of tCAL_L. This pin is active in both ECM and non-ECM. In ECM, this pin is logically OR'd with the CAL Bit (Addr: 0h, Bit 15) in the Control Register. Therefore, both pin and bit must be set low and then either can be set high to execute an on-command calibration. |
U3
V3 |
PDI
PDQ |
|
Power-down I channel and Q-channel. Setting either input to logic-high powers down the respective I-channel or Q-channel converter. Setting either input to logic-low brings the respective I channel or Q-channel converter to a fully operational state after a finite time delay. This pin is active in both ECM and non-ECM. In the ECM, either this pin or the PDI and PDQ bit in the Control Register can be used to power-down the I channel and Q channel (Addr: 0h, Bit 11 and Bit 10), respectively. |
| W3 |
RSV |
NONE |
Reserved: This pin is used for internal purposes and must be connected to GND through a 100-KΩ resistor. |
| W4 |
DDRPh |
|
DDR phase select. This input, when logic-low, selects the 0-degree data-to-DCLK phase relationship; when logic-high, the input selects the 90-degree data-to-DCLK phase relationship. This pin only has an effect when the chip is in 1:2 demuxed mode; for example, when the NDM pin is set to logic-low. In ECM, this input is ignored and the DDR phase is selected through the DPS bit of the Control Register (Addr: 0h, bit 14); the default is 0-degree data-to-DCLK phase relationship. |
| Y3 |
FSR |
|
Full-scale input range select. In non-ECM, when this input is set to logic-low or logic-high, the full-scale differential input range for both I-channel and Q-channel inputs is set to the lower or higher value, respectively. In ECM, this input is ignored and the full-scale range of the I-channel and Q-channel inputs is independently determined by the setting of Addr: 3h and Addr: Bh, respectively. Note that the higher and lower FSR value in non-ECM does not precisely correspond to the maximum and minimum available selection in ECM; in ECM, the selection range is greater.
|
| POWER AND GROUND PINS |
A1, A7, B2, B7, C6, D4, D5, E4, K1, L1, T4, U4, U5, V4, V5, W2, W7, Y1, Y7,
AA2thru AL11 |
GND |
NONE |
Analog ground return |
| A2, A6, B6, C7, D1, D8, D9, E1, F1, H4, N4, R1, T1, U8, U9, W6, Y2, Y6 |
VA |
NONE |
Analog power supply. This supply is tied to the ESD ring. Therefore, it must be powered up before or with any other supply. |
| A8, B9, C8, V8, W9, Y8 |
VE |
NONE |
Power supply for the digital encoder |
| A9, B8, C9, V9, W8, Y9 |
GNDE |
NONE |
Ground return for the digital encoder |
| A10, A13, A17, A20, B10 B18, B19, B20, C10, C17, D10, D13, D16, E17, F17, F20, M17, M20, U10,U13, U17, V10, V17, V18, W10, W18, W19, W20, Y10, Y13, Y17, Y20 |
GNDDR |
NONE |
Ground return for the output driver |
| A11, A15, C18, D11, D15, D17, J17, J20, R17, R20, T17, U11, U15, U16, Y11, Y15 |
VDR |
NONE |
Power supply for the output drivers |
| D7, J4, K2 |
VbiasI |
NONE |
Bias voltage I channel. This is an externally decoupled bias voltage for the I channel. Each pin must individually be decoupled with a 100-nF capacitor via a low resistance, low inductance path to GND. |
| E3 |
RSV1 |
NONE |
Reserved: This pin is used for internal purposes. This pin must individually be decoupled with a 100-nF capacitor via a low resistance, low inductance path to GND. |
| F2, G2, H3, J2, K4, L4, M2, N3, P2, R2, T2, T3, U1 |
GNDTC |
NONE |
Analog ground return for the track-and-hold and clock circuitry |
| L2, M4, U7 |
VbiasQ |
NONE |
Bias voltage Q channel. This is an externally decoupled bias voltage for the Q channel. Each pin must individually be decoupled with a 100-nF capacitor via a low resistance, low inductance path to GND. |
| F4 |
RSV2 |
NONE |
Reserved: This pin is used for internal purposes. This pin must individually be decoupled with a 100-nF capacitor via a low resistance, low inductance path to GND. |
| G1, G3, G4, H2, J3, K3, L3, M3, N2, P1, P3, P4, R3, R4 |
VTC |
NONE |
Analog power supply for the track-and-hold and clock circuitry |
| HIGH-SPEED DIGITAL OUTPUTS |
A18/A19
B17/C16
A16/B16
B15/C15
C14/D14
A14/B14
B13/C13
C12/D12
A12/B12
B11/C11
·
Y18/Y19
W17/V16
Y16/W16
W15/V15
V14/U14
Y14/W14
W13/V13
V12/U12
Y12/W12
W11/V11 |
DId9+, Dld9–
DId8+, Dld8–
DId7+, Dld7–
DId6+, Dld6–
DId5+, Dld5–
DId4+, Dld4–
DId3+, Dld3–
DId2+, Dld2–
DId1+, Dld1–
DId0+, Dld0–
·
DQd9+, DQld9–
DQd8+, DQd8–
DQd7+, DQd7–
DQd6+, DQd6–
DQd5+, DQd5–
DQd4+, DQd4–
DQd3+, DQd3–
DQd2+, DQd2–
DQd1+, DQd1–
DQd0+, DQd0– |
|
Delayed I-channel and Q-channel digital data outputs. In non-demux mode, these outputs are tri-stated. In Demux Mode, these outputs provide ½ the data at ½ the sampling clock rate, synchronized with the non-delayed data, that is, the other ½ of the data which was sampled one clock cycle later. Compared with the DI and DQ outputs, these outputs represent the earlier time samples. Each of these outputs must always be terminated with a 100-Ω differential resistor placed as closely as possible to the differential receiver. |
J18/J19
H19/H20
H17/H18
G19/G20
G17/G18
F18/F19
E19/E20
D19/D20
D18/E18
C19/C20
·
M18/M19
N19/N20
N17/N18
P19/P20
P17/P18
R18/R19
T19/T20
U19/U20
U18/T18
V19/V20 |
DI9+, DI9–
DI8+, DI8–
DI7+, DI7–
DI6+, DI6–
DI5+, DI5–
DI4+, DI4–
DI3+, DI3–
DI2+, DI2–
DI1+, DI1–
DI0+, DI0–
·
DI9+, DI9–
DQ8+, DQ8–
DQ7+, DQ7–
DQ6+, DQ6–
DQ5+, DQ5–
DQ4+, DQ4–
DQ3+, DQ3–
DQ2+, DQ2–
DQ1+, DQ1–
DQ0+, DQ0– |
|
I-channel and Q-channel digital data outputs. In non-demux mode, this LVDS data is transmitted at the sampling clock rate. In demux mode, these outputs provide ½ the data at ½ the sampling clock rate, synchronized with the delayed data, that is, the other ½ of the data, which was sampled one clock cycle earlier. Compared with the DId and DQd outputs, these outputs represent the later time samples. Always terminate each of these outputs with a 100-Ω differential resistor placed as closely as possible to the differential receiver |
K17/K18
L17/L18 |
ORI+, ORI–
ORQ+, ORQ– |
|
Out-of-range output for the I channel and Q channel. This differential output is asserted logic-high while the over- or under-range condition exists, that is, the differential signal at each respective analog input exceeds the full-scale value. Each OR results refers to the current data, with which it is clocked out. Always terminate each of these outputs with a 100-Ω differential resistor placed as closely as possible to the differential receiver. |
K19/K20
L19/L20 |
DCLKI+, DLKI–
DCLKQ+, DLKQ– |
|
Data clock output for the I-channel and Q-channel data bus. These differential clock outputs are used to latch the output data and must always be terminated with a 100-Ω differential resistor. Delayed and non-delayed data outputs are supplied synchronously to this signal. In 1:2 demux mode or non-demux mode, this signal is at ¼ or ½ the input clock rate, respectively. DCLKI+, DLKI– and DCLKQ+, DLKQ– are always in phase with each other, unless one channel is powered down, and they do not require a pulse from DCLK_RST+, DCLK_RST– to become synchronized. |
