SNAS305J July   2005  – March 2016 ADC121S021

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
      1. 9.4.1 Normal Mode
      2. 9.4.2 Shutdown Mode
  10. 10Applications Information
    1. 10.1 Application Information
      1. 10.1.1 Using the ADC121S021
        1. 10.1.1.1 Determining Throughput
      2. 10.1.2 ADC121S021 Transfer Function
      3. 10.1.3 Analog Inputs
      4. 10.1.4 Digital Inputs And Outputs
      5. 10.1.5 Power Management
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Power Supply Noise Considerations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Device Nomenclature
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)(3)
MIN MAX UNIT
Analog supply voltage, VA –0.3 6.5 V
Voltage on any digital pin to GND –0.3 6.5 V
Voltage on any analog pin to GND –0.3 VA + 0.3 V
Input current at any pin(4) ±10 mA mA
Package input current(4) ±20 mA mA
Power consumption at TA = 25°C See (5)
Junction temperature, TJ 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
(3) All voltages are measured with respect to GND = 0 V, unless otherwise specified.
(4) When the input voltage at any pin exceeds the power supply (that is, VIN < GND or VIN > VA), the current at that pin must be limited to 10 mA. The 20-mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two. The absolute maximum rating specification does not apply to the VA pin. The current into the VA pin is limited by the Analog Supply Voltage specification.
(5) The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (RθJA), and the ambient temperature (TA), and can be calculated using the formula PDmax = (TJmax – TA) / RθJA. The values for maximum power dissipation listed above is reached only when the device is operated in a severe fault condition (for example, when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions must always be avoided.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)(2) ±3500 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(3) ±1250
Machine mode (MM)(4) ±300
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) HBM is 100-pF capacitor discharged through a 1.5-kΩ resistor.
(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(4) Machine model is 220-pF discharged through 0 Ω.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Operating temperature, TA –40 85 °C
Supply voltage, VA 2.7 5.25 V
Digital input pins voltage(2) –0.3 5.25 V
Analog input pins voltage 0 VA V
Clock frequency 0.025 20 MHz
Sample rate 1 Msps
(1) All voltages are measured with respect to GND = 0 V, unless otherwise specified.
(2) Regardless of supply voltage

7.4 Thermal Information

THERMAL METRIC(1)(2) ADC121S021 UNIT
DBV (SOT-23) NGF (WSON)
6 PINS 6 PINS
RθJA Junction-to-ambient thermal resistance 185 83.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 156.5 72.1 °C/W
RθJB Junction-to-board thermal resistance 29.6 24.8 °C/W
ψJT Junction-to-top characterization parameter 33.8 3.4 °C/W
ψJB Junction-to-board characterization parameter 29.1 24.7 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — 14.8 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
(2) Soldering process must comply with Reflow Temperature Profile specifications. See http://www.ti.com/lit/SNOA549. Reflow temperature profiles are different for lead-free and non-lead-free packages.

7.5 Electrical Characteristics

VA = 2.7 V to 5.25 V, fSCLK = 1 MHz to 4 MHz, fSAMPLE = 50 ksps to 200 ksps, CL = 15 pF, unless otherwise noted. Typical limits apply for TA = 25°C; minimum and maximum limits apply for TA = –40°C to 85°C, unless otherwise noted. All limits(1)(2)(2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC CONVERTER CHARACTERISTICS
Resolution with
no missing codes		 TA = –40°C to 85°C 12 Bits
INL Integral non-linearity VA = 2.7 V to 3.6 V TA = 25°C –0.4 0.45 LSB
TA = –40°C to 85°C –1 1
VA = 4.75 V to 5.25 V TA = 25°C –0.4 0.55 LSB
DNL Differential non-linearity VA = 2.7 V to 3.6 V TA = 25°C –0.25 0.45 LSB
TA = –40°C to 85°C –0.8 1
VA = 4.75 V to 5.25 V TA = 25°C –0.3 0.6 LSB
VOFF Offset error VA = 2.7 V to 3.6 V –0.18 ±1.2 LSB
VA = 4.75 V to 5.25 V TA = 25°C –0.26
GE Gain error VA = 2.7 V to 3.6 V –0.75 ±1.5 LSB
VA = 4.75 V to 5.25 V TA = 25°C –1.6
DYNAMIC CONVERTER CHARACTERISTICS
SINAD Signal-to-noise plus
distortion ratio		 VA = 2.7 V to 5.25 V, fIN = 100 kHz, –0.02 dBFS 70 72 dBFS
SNR Signal-to-noise ratio VA = 2.7 V to 5.25 V, fIN = 100 kHz, –0.02 dBFS 70.8 72.3 dBFS
THD Total harmonic distortion VA = 2.7 V to 5.25 V, fIN = 100 kHz, –0.02 dBFS –83 dBFS
SFDR Spurious-free dynamic range VA = 2.7 V to 5.25 V, fIN = 100 kHz, –0.02 dBFS 85 dB
ENOB Effective number of bits VA = 2.7 V to 5.25 V, fIN = 100 kHz, –0.02 dBFS 11.3 11.7 Bits
IMD Intermodulation distortion, second order terms VA = 5.25 V, fa = 103.5 kHz, fb = 113.5 kHz –83 dBFS
Intermodulation distortion,
third order terms		 VA = 5.25 V, fa = 103.5 kHz, fb = 113.5 kHz –82 dBFS
FPBW –3-dB full power bandwidth VA = 5 V 11 MHz
VA = 3 V 8
ANALOG INPUT CHARACTERISTICS
VIN Input range TA = 25°C 0 VA V
IDCL DC leakage current –1 1 µA
CINA Input capacitance Track Mode 30 pF
Hold Mode 4
DIGITAL INPUT CHARACTERISTICS
VIH Input high voltage VA = 5.25 V TA = –40°C to 85°C 2.4 V
VA = 3.6 V TA = –40°C to 85°C 2.1
VIL Input low voltage VA = 5 V TA = –40°C to 85°C 0.8 V
VA = 3 V TA = –40°C to 85°C 0.4
IIN Input current VIN = 0 V or VA ±0.1 ±1 µA
CIND Digital input capacitance 2 4 pF
DIGITAL OUTPUT CHARACTERISTICS
VOH Output high voltage ISOURCE = 200 µA VA – 0.2 VA – 0.07 V
ISOURCE = 1 mA VA – 0.1
VOL Output low voltage ISINK = 200 µA 0.03 0.4 V
ISINK = 1 mA 0.1
IOZH, IOZL TRI-STATE® leakage current ±0.1 ±10 µA
COUT TRI-STATE output capacitance 2 4 pF
Output coding Straight (Natural) Binary
POWER SUPPLY CHARACTERISTICS
VA Supply voltage 2.7 5.25 V
IA Supply current, normal mode
(operational, CS low)		 VA = 5.25 V, fSAMPLE = 200 ksps 1.5 2.8 mA
VA = 3.6 V, fSAMPLE = 200 ksps 0.4 1.2
Supply current, shutdown
(CS high)		 fSCLK = 0 MHz, VA = 5.25 V, fSAMPLE = 0 ksps 500 nA
fSCLK = 4 MHz, VA = 5.25 V, fSAMPLE= 0 ksps 60 µA
PD Power consumption,
normal mode
(operational, CS low)		 VA = 5.25 V 7.9 14.7 mW
VA = 3.6 V 1.5 4.3
Power consumption, shutdown
(CS high)		 fSCLK = 0 MHz, VA = 5.25 V, fSAMPLE = 0 ksps 2.6 µW
VA = 5.25 V, fSCLK = 4 MHz, fSAMPLE= 0 ksps 315
AC ELECTRICAL CHARACTERISTICS
fSCLK Clock frequency(3) 1 4 MHz
fS Sample rate(3) 50 200 ksps
DC SCLK duty cycle fSCLK = 4 MHz 40% 50% 60%
tACQ Minimum acquisition time 350 ns
tQUIET Minimum quiet time(4) 50 ns
tAD Aperture delay 3 ns
tAJ Aperture jitter 30 ps
(1) Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).
(2) Data sheet min/max specification limits are ensured by design, test, or statistical analysis.
(3) This is the frequency range over which the electrical performance is ensured. The device is functional over a wider range which is specified under Operating Ratings.
(4) Required by bus relinquish and the start of the next conversion.

7.6 Timing Requirements

The following specifications apply for VA = 2.7 V to 5.25 V, GND = 0 V, fSCLK = 1 MHz to 4 MHz, CL = 25 pF, fSAMPLE = 50 ksps to 200 ksps, all limits TA = –40°C to 85°C unless otherwise noted.
MIN TYP MAX UNIT
tCS Minimum CS pulse width 10 ns
tSU CS to SCLK setup time 10 ns
tEN Delay from CS until SDATA TRI-STATE disabled(1) 20 ns
tACC Data access time after SCLK falling edge(2) VA = 2.7 V to 3.6 V 40 ns
VA = 4.75 V to 5.25 V 20
tCL SCLK low pulse width 0.4 × tSCLK ns
tCH SCLK high pulse width 0.4 × tSCLK
tH SCLK to data valid hold time VA = 2.7 V to 3.6 V 7 ns
VA = 4.75 V to 5.25 V 5
tDIS SCLK falling edge to
SDATA high impedance(3)		 VA = 2.7 V to 3.6 V 6 25 ns
VA = 4.75 V to 5.25 V 5 25
tPOWER-UP Power-up time from full power-down TA = 25°C 1 µs
(1) Measured with the timing test circuit shown in Figure 12 and defined as the time taken by the output signal to cross 1 V.
(2) Measured with the timing test circuit shown in Figure 12 and defined as the time taken by the output signal to cross 1 V or 2 V.
(3) tDIS is derived from the time taken by the outputs to change by 0.5 V with the timing test circuit shown in Figure 12. The measured number is then adjusted to remove the effects of charging or discharging the output capacitance. This means that tDIS is the true bus relinquish time, independent of the bus loading.
ADC121S021 20145106.gif Figure 1. ADC121S021 Serial Timing Diagram

7.7 Typical Characteristics

TA = 25°C, fSAMPLE = 50 ksps to 200 ksps, fSCLK = 1 MHz to 4 MHz, fIN = 100 kHz unless otherwise stated.
ADC121S021 20145120.png
fSCLK = 1 MHz
Figure 2. DNL
ADC121S021 20145160.png
fSCLK = 4 MHz
Figure 4. DNL
ADC121S021 20145165.png Figure 6. DNL vs Clock Frequency
ADC121S021 20145163.png Figure 8. SNR vs Clock Frequency
ADC121S021 20145168.png
Figure 10. THD vs Clock Frequency
ADC121S021 20145121.png
fSCLK = 1 MHz
Figure 3. INL
ADC121S021 20145161.png
fSCLK = 4 MHz
Figure 5. INL
ADC121S021 20145166.png Figure 7. INL vs Clock Frequency
ADC121S021 20145167.png Figure 9. SFDR vs Clock Frequency
ADC121S021 20145155.png
fSCLK = 4 MHz
Figure 11. Power Consumption vs Throughput
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