SNAS333E August 2005 – December 2015 ADC128S052 , ADC128S052-Q1
PRODUCTION DATA.
5 Pin Configuration and Functions
PW Package
16-Pin TSSOP
Top View
Pin Functions
| PIN | TYPE | DESCRIPTION | |
|---|---|---|---|
| NO. | NAME | ||
| 1 | CS | Digital I/O | Chip select. On the falling edge of CS, a conversion process begins. Conversions continue as long as CS is held low. |
| 2 | VA | Power Supply | Positive analog supply pin. This voltage is also used as the reference voltage. This pin must be connected to a quiet 2.7-V to 5.25-V source and bypassed to GND with 1-µF and 0.1-µF monolithic ceramic capacitors located within 1 cm of the power pin. |
| 3 | AGND | Power Supply | The ground return for the analog supply and signals. |
| 4 | IN0 to IN7 | Analog I/O | Analog inputs. These signals can range from 0 V to VREF. |
| 5 | |||
| 6 | |||
| 7 | |||
| 8 | |||
| 9 | |||
| 10 | |||
| 11 | |||
| 12 | DGND | Power Supply | The ground return for the digital supply and signals. |
| 13 | VD | Power Supply | Positive digital supply pin. This pin must be connected to a 2.7-V to VA supply, and bypassed to GND with a 0.1-µF monolithic ceramic capacitor located within 1 cm of the power pin. |
| 14 | DIN | Digital I/O | Digital data input. The control register of the ADC128S052 is loaded through this pin on rising edges of the SCLK pin. |
| 15 | DOUT | Digital I/O | Digital data output. The output samples are clocked out of this pin on the falling edges of the SCLK pin. |
| 16 | SCLK | Digital I/O | Digital clock input. The ensured performance range of frequencies for this input is 3.2 MHz to 8 MHz. This clock directly controls the conversion and readout processes. |