SNAS333E August 2005 – December 2015 ADC128S052 , ADC128S052-Q1
PRODUCTION DATA.
6 Specifications
6.1 Absolute Maximum Ratings
See (1)(2)(3)| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| Analog Supply Voltage VA | –0.3 | 6.5 | V | |
| Digital Supply Voltage VD | –0.3 | VA + 0.3, max 6.5 | V | |
| Voltage on Any Pin to GND | –0.3 | VA + 0.3 | V | |
| Input Current at Any Pin(4) | ±10 | mA | ||
| Package Input Current(4) | ±20 | mA | ||
| Power Dissipation at TA = 25°C | See (5) | |||
| Junction Temperature | +150 | °C | ||
| Storage Temperature, Tstg | −65 | 150 | °C | |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, contact the TI Sales Office/Distributors for availability and specifications.
(3) For soldering specifications: see product folder at www.ti.com and SNOA549.
(4) When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND or VIN > VA or VD), the current at that pin must be limited to 10 mA. The 20-mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two.
(5) The absolute maximum junction temperature (TJMAX) for this device is 150°C. The maximum allowable power dissipation is dictated by TJMAX, the junction-to-ambient thermal resistance (RθJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJMAX − TA)/RθJA. In the 16-pin TSSOP, RθJA is 110°C/W, so PDMAX = 1,200 mW at 25°C and 625 mW at the maximum operating ambient temperature of 105°C. Note that the power consumption of this device under normal operation is a maximum of
12 mW. The values for maximum power dissipation listed above is reached only when the ADC128S052 is operated in a severe fault condition (for example, when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Such conditions must always be avoided.
12 mW. The values for maximum power dissipation listed above is reached only when the ADC128S052 is operated in a severe fault condition (for example, when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Such conditions must always be avoided.
6.2 ESD Ratings – Commercial
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)(2) | ±2500 | V |
| Machine model (MM)(3) | ±250 | |||
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) Human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor.
(3) Machine model is a 220-pF discharged through ZERO Ω.
6.3 ESD Ratings – Automotive
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human-body model (HBM), per AEC Q100-002(1) | ±2500 | V |
| Charged-device model (CDM), per AEC Q100-011 | ±250 | |||
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.4 Recommended Operating Conditions
See (1)| MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|
| Operating Temperature | ADC128S052 | −40 | TA | 105 | °C |
| ADC128S052-Q1 | −40 | TA | 125 | °C | |
| VA Supply Voltage | 2.7 | 5.25 | V | ||
| VD Supply Voltage | 2.7 | VA | V | ||
| Digital Input Voltage | 0 | VA | V | ||
| Analog Input Voltage | 0 | VA | V | ||
| Clock Frequency | 50 | 1600 | kHz | ||
(1) All voltages are measured with respect to GND = 0 V, unless otherwise specified.
6.5 Thermal Information
| THERMAL METRIC(1) | ADC128S052, ADC128S052-Q1 | UNIT | |
|---|---|---|---|
| PW (TSSOP) | |||
| 16 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 110 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 42 | °C/W |
| RθJB | Junction-to-board thermal resistance | 56 | °C/W |
| ψJT | Junction-to-top characterization parameter | 5 | °C/W |
| ψJB | Junction-to-board characterization parameter | 55 | °C/W |
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
6.6 Electrical Characteristics
The following specifications apply for AGND = DGND = 0 V, fSCLK = 3.2 MHz to 8 MHz, fSAMPLE = 200 kSPS to 500 kSPS, CL = 50 pF, unless otherwise noted. Maximum and minimum limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.(2)| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX(1) | UNIT | |
|---|---|---|---|---|---|---|
| STATIC CONVERTER CHARACTERISTICS | ||||||
| Resolution with No Missing Codes | 12 | Bits | ||||
| INL | Integral Non-Linearity (End Point Method) | VA = VD = 3 V | ±0.3 | ±1 | LSB | |
| VA = VD = 5 V | ±0.4 | ±1 | LSB | |||
| DNL | Differential Non-Linearity | VA = VD = 3 V | 0.3 | 0.9 | LSB | |
| −0.7 | −0.2 | LSB | ||||
| VA = VD = 5 V | 0.6 | 1.3 | LSB | |||
| −0.9 | −0.4 | LSB | ||||
| VOFF | Offset Error | VA = VD = 3 V | 0.8 | ±2.3 | LSB | |
| VA = VD = 5 V | 1.2 | ±2.3 | LSB | |||
| OEM | Offset Error Match | VA = VD = 3 V | ±0.05 | ±1.5 | LSB | |
| VA = VD = 5 V | ±0.2 | ±1.5 | LSB | |||
| FSE | Full Scale Error | VA = VD = 3 V | 0.6 | ±2.0 | LSB | |
| VA = VD = 5 V | 0.3 | ±2.0 | LSB | |||
| FSEM | Full Scale Error Match | VA = VD = 3 V | ±0.05 | ±1.5 | LSB | |
| VA = VD = 5 V | ±0.2 | ±1.5 | LSB | |||
| DYNAMIC CONVERTER CHARACTERISTICS | ||||||
| FPBW | Full Power Bandwidth (−3 dB) | VA = VD = 3 V | 8 | MHz | ||
| VA = VD = 5 V | 11 | MHz | ||||
| SINAD | Signal-to-Noise Plus Distortion Ratio | VA = VD = 3 V, fIN = 40.2 kHz, −0.02 dBFS |
70 | 73 | dB | |
| VA = VD = 5 V, fIN = 40.2 kHz, −0.02 dBFS |
70 | 73 | dB | |||
| SNR | Signal-to-Noise Ratio | VA = VD = 3 V, fIN = 40.2 kHz, −0.02 dBFS |
70.8 | 73 | dB | |
| VA = VD = 5 V, fIN = 40.2 kHz, −0.02 dBFS |
70.8 | 73 | dB | |||
| THD | Total Harmonic Distortion | VA = VD = 3 V, fIN = 40.2 kHz, −0.02 dBFS |
−90 | −74 | dB | |
| VA = VD = 5 V, fIN = 40.2 kHz, −0.02 dBFS |
−89 | −74 | dB | |||
| SFDR | Spurious-Free Dynamic Range | VA = VD = 3 V, fIN = 40.2 kHz, −0.02 dBFS |
75 | 92 | dB | |
| VA = VD = 5 V, fIN = 40.2 kHz, −0.02 dBFS |
75 | 91 | dB | |||
| ENOB | Effective Number of Bits | VA = VD = 3 V, fIN = 40.2 kHz |
11.3 | 11.8 | Bits | |
| VA = VD = 5 V, fIN = 40.2 kHz, −0.02 dBFS |
11.3 | 11.8 | Bits | |||
| ISO | Channel-to-Channel Isolation | VA = VD = 3 V, fIN = 20 kHz |
81 | dB | ||
| VA = VD = 5 V, fIN = 20 kHz, −0.02 dBFS |
81 | dB | ||||
| IMD | Intermodulation Distortion, Second Order Terms | VA = VD = 3 V, fa = 19.5 kHz, fb = 20.5 kHz |
−98 | dB | ||
| VA = VD = 5 V, fa = 19.5 kHz, fb = 20.5 kHz |
−91 | dB | ||||
| Intermodulation Distortion, Third Order Terms | VA = VD = 3 V, fa = 19.5 kHz, fb = 20.5 kHz |
−89 | dB | |||
| VA = VD = 5 V, fa = 19.5 kHz, fb = 20.5 kHz |
−88 | dB | ||||
| ANALOG INPUT CHARACTERISTICS | ||||||
| VIN | Input Range | 0 | VA | V | ||
| IDCL | DC Leakage Current | ±1 | µA | |||
| CINA | Input Capacitance | Track Mode | 33 | pF | ||
| Hold Mode | 3 | pF | ||||
| DIGITAL INPUT CHARACTERISTICS | ||||||
| VIH | Input High Voltage | VA = VD = 2.7 V to 3.6 V | 2.1 | V | ||
| VA = VD = 4.75 V to 5.25 V | 2.4 | V | ||||
| VIL | Input Low Voltage | VA = VD = 2.7 V to 5.25 V | 0.8 | V | ||
| IIN | Input Current | VIN = 0 V or VD | ±0.01 | ±1 | µA | |
| CIND | Digital Input Capacitance | 2 | 4 | pF | ||
| DIGITAL OUTPUT CHARACTERISTICS | ||||||
| VOH | Output High Voltage | ISOURCE = 200 µA, VA = VD = 2.7 V to 5.25 V |
VD − 0.5 | V | ||
| VOL | Output Low Voltage | ISINK = 200 µA to 1.0 mA, VA = VD = 2.7 V to 5.25 V |
0.4 | V | ||
| IOZH, IOZL | Hi-Impedance Output Leakage Current | VA = VD = 2.7 V to 5.25 V | ±1 | µA | ||
| COUT | Hi-Impedance Output Capacitance(2) | 2 | 4 | pF | ||
| Output Coding | Straight (Natural) Binary | |||||
| POWER SUPPLY CHARACTERISTICS (CL = 10 pF) | ||||||
| VA, VD | Analog and Digital Supply Voltages | VA ≥ VD | 2.7 | 5.25 | V | |
| IA + ID | Total Supply Current Normal Mode ( CS low) |
VA = VD = 2.7 V to 3.6 V, fSAMPLE = 500 kSPS, fIN = 40 kHz |
0.54 | 1.2 | mA | |
| VA = VD = 4.75 V to 5.25 V, fSAMPLE = 500 kSPS, fIN = 40 kHz |
1.74 | 2.6 | mA | |||
| Total Supply Current Shutdown Mode (CS high) |
VA = VD = 2.7 V to 3.6 V, fSCLK = 0 kSPS |
20 | nA | |||
| VA = VD = 4.75 V to 5.25 V, fSCLK = 0 kSPS |
50 | nA | ||||
| PC | Power Consumption Normal Mode ( CS low) |
VA = VD = 3 V fSAMPLE = 500 kSPS, fIN = 40 kHz |
1.6 | 3.6 | mW | |
| VA = VD = 5.0 V fSAMPLE = 500 kSPS, fIN = 40 kHz |
8.7 | 13.0 | mW | |||
| Power Consumption Shutdown Mode (CS high) |
VA = VD = 3 V fSCLK = 0 kSPS |
0.06 | µW | |||
| VA = VD = 5 V fSCLK = 0 kSPS |
0.25 | µW | ||||
| AC ELECTRICAL CHARACTERISTICS | ||||||
| fSCLKMIN | Minimum Clock Frequency | VA = VD = 2.7 V to 5.25 V | 3.2 | 0.8 | MHz | |
| fSCLK | Maximum Clock Frequency | VA = VD = 2.7 V to 5.25 V | 16 | 8 | MHz | |
| fS | Sample Rate Continuous Mode |
VA = VD = 2.7 V to 5.25 V | 200 | 50 | kSPS | |
| 1000 | 500 | kSPS | ||||
| tCONVERT | Conversion (Hold) Time | VA = VD = 2.7 V to 5.25 V | 13 | SCLK cycles | ||
| DC | SCLK Duty Cycle | VA = VD = 2.7 V to 5.25 V | 40% | 30% | ||
| 70% | 60% | |||||
| tACQ | Acquisition (Track) Time | VA = VD = 2.7 V to 5.25 V | 3 | SCLK cycles | ||
| Throughput Time | Acquisition Time + Conversion Time VA = VD = 2.7 V to 5.25 V |
16 | SCLK cycles | |||
| tAD | Aperture Delay | VA = VD = 2.7 V to 5.25 V | 4 | ns | ||
(1) Tested limits are ensured to TI's AOQL (Average Outgoing Quality Level).
(2) Data sheet minimum and maximum specification limits are ensured by design, test, or statistical analysis.
6.7 Timing Specifications
The following specifications apply for VA = VD = 2.7 V to 5.25 V, AGND = DGND = 0 V, fSCLK = 3.2 MHz to 8 MHz, fSAMPLE = 200 kSPS to 500 kSPS, and CL = 50 pF. Maximum and minimum limits apply for TA = TMIN to TMAX; all other limits TA = 25°C. See Figure 1, Figure 2, and Figure 3.| MIN | NOM | MAX(1) | UNIT | |||
|---|---|---|---|---|---|---|
| tCSH | CS Hold Time after SCLK Rising Edge | 10 | 0 | ns | ||
| tCSS | CS Set-up Time prior to SCLK Rising Edge | 10 | 4.5 | ns | ||
| tEN | CS Falling Edge to DOUT enabled | 5 | 30 | ns | ||
| tDACC | DOUT Access Time after SCLK Falling Edge | 17 | 27 | ns | ||
| tDHLD | DOUT Hold Time after SCLK Falling Edge | 4 | ns | |||
| tDS | DIN Set-up Time prior to SCLK Rising Edge | 10 | 3 | ns | ||
| tDH | DIN Hold Time after SCLK Rising Edge | 10 | 3 | ns | ||
| tCH | SCLK High Time | 0.4 × tSCLK | ns | |||
| tCL | SCLK Low Time | 0.4 × tSCLK | ns | |||
| tDIS | CS Rising Edge to DOUT High-Impedance | DOUT falling | 2.4 | 20 | ns | |
| DOUT rising | 0.9 | 20 | ns | |||
(1) Tested limits are ensured to TI's AOQL (Average Outgoing Quality Level).
Figure 1. ADC128S052 Operational Timing Diagram
Figure 2. ADC128S052 Serial Timing Diagram
Figure 3. SCLK and CS Timing Parameters
6.8 Typical Characteristics
TA = 25°C, fSAMPLE = 500 kSPS, fSCLK = 8 MHz, fIN = 40.2 kHz unless otherwise stated
Figure 4. DNL
Figure 6. INL
Figure 5. DNL
Figure 7. INL
Figure 8. DNL vs Supply
Figure 10. SNR vs Supply
| VA = 5 V |
Figure 16. INL vs SCLK Duty Cycle
Figure 18. THD vs SCLK Duty Cycle
Figure 20. DNL vs SCLK
Figure 22. SNR vs SCLK
Figure 24. ENOB vs SCLK
Figure 26. INL vs Temperature
Figure 28. THD vs Temperature
Figure 30. SNR vs Input Frequency
Figure 32. ENOB vs Input Frequency
Figure 9. INL vs Supply
Figure 11. THD vs Supply
| VA = 5 V |
Figure 17. SNR vs SCLK Duty Cycle
Figure 19. ENOB vs SCLK Duty Cycle
Figure 21. INL vs SCLK
Figure 23. THD vs SCLK
Figure 25. DNL vs Temperature
Figure 27. SNR vs Temperature
Figure 29. ENOB vs Temperature
Figure 31. THD vs Input Frequency
Figure 33. Power Consumption vs SCLK