Simplified schematics of the ADC128S102-SEP in both track and hold operation are provided in Figure 7-3 and Figure 7-4, respectively. In Figure 7-3, the ADC128S102-SEP is in track mode: switch SW1 connects the sampling capacitor to one of eight analog input channels through the multiplexer, and SW2 balances the comparator inputs. The ADC128S102-SEP is in this state for the first three SCLK cycles after CS is brought low.

Figure 7-3 ADC128S102-SEP in Track Mode

Figure 7-4 shows the ADC128S102-SEP in hold mode: switch SW1 connects the sampling capacitor to ground, maintaining the sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs the charge-redistribution DAC to add or subtract fixed amounts of charge to or from the sampling capacitor until the comparator is balanced. When the comparator is balanced, the digital word supplied to the DAC is the digital representation of the analog input voltage. The ADC128S102-SEP is in this state for the last 13 SCLK cycles after CS is brought low.

Figure 7-4 ADC128S102-SEP in Hold Mode