ANALOG I/O |
IN0 to IN7 |
4 |
Input (Analog) |
Analog inputs. These signals can range from 0 V to VREF. |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
DIGITAL I/O |
CS |
1 |
Input (Digital) |
Chip select. On the falling edge of CS, a conversion process begins. Conversions continue as long as CS is held low. |
DIN |
14 |
Input (Digital) |
Digital data input. The ADC128S102QML-SP's Control Register is loaded through this pin on rising edges of the SCLK pin. |
DOUT |
15 |
Output (Digital) |
Digital data output. The output samples are clocked out of this pin on the falling edges of the SCLK pin. |
SCLK |
16 |
Input (Digital) |
Digital clock input. The specified performance range of frequencies for this input is 0.8 MHz to 16 MHz. This clock directly controls the conversion and readout processes. |
POWER SUPPLY |
AGND |
3 |
Ground |
The ground return for the analog supply and signals. |
DGND |
12 |
Ground |
The ground return for the digital supply and signals. |
VA |
2 |
Supply |
Positive analog supply pin. This voltage is also used as the reference voltage. This pin should be connected to a quiet 2.7 V to 5.25 V source and bypassed to GND with 1-µF and 0.1-µF monolithic ceramic capacitors located within 1 cm of the power pin. |
VD |
13 |
Supply |
Positive digital supply pin. This pin should be connected to a 2.7 V to VA supply, and bypassed to GND with a 0.1-µF monolithic ceramic capacitor located within 1 cm of the power pin. |