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SNAS480N May 2010 – August 2015 ADC12D1000 , ADC12D1600

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

	MIN	MAX	UNIT
Supply Voltage (V_A, V_TC, V_DR, V_E)		2.2	V
Supply Difference max(V_A/TC/DR/E) - min(V_A/TC/DR/E)	0	100	mV
Voltage on Any Input Pin (except V_IN+/-)	–0.15	V_A + 0.15	V
V_IN+/- Voltage Range	–0.5	2.5	V
Ground Difference max(GND_TC/DR/E) - min(GND_TC/DR/E)	0	100	mV
Input Current at Any Pin⁽²⁾	–50	50	mA
ADC12D1000 Package Power Dissipation at T_A ≤ 75°C⁽²⁾		4.06	W
ADC12D1600 Package Power Dissipation at T_A ≤ 65°C⁽²⁾		4.37	W
Storage Temperature, T_stg	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) When the input voltage at any pin exceeds the power supply limits, that is, less than GND or greater than V_A, the current at that pin should be limited to 50 mA. In addition, overvoltage at a pin must adhere to the maximum voltage limits. Simultaneous overvoltage at multiple pins requires adherence to the maximum package power dissipation limits. These dissipation limits are calculated using JEDEC JESD51-7 thermal model. Higher dissipation may be possible based on specific customer thermal situation and specified package thermal resistances from junction to case.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2500	V
		Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1000
		Machine Model	±250

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

			MIN	MAX	UNIT
T_A	Ambient Temperature	ADC12D1000 (Standard JEDEC thermal model)	–40	75	°C
		ADC12D1600 (Standard JEDEC thermal model)	–40	65	°C
		ADC12D1x00 (Enhanced thermal model or heatsink)	–40	85	°C
T_J	Junction Temperature Range⁽⁴⁾	ADC12D1000 Junction Temperature Range		140	°C
T_J	Junction Temperature Range⁽⁴⁾	ADC12D1600 Junction Temperature Range		135	°C
Supply Voltage (V_A, V_TC, V_E)			1.8	2	V
Driver Supply Voltage (V_DR)			1.8	V_A	V
V_IN+/- Voltage Range⁽²⁾		(DC-coupled)	–0.4	2.4	V
V_IN+/- Differential Voltage⁽³⁾		(DC-coupled at 100% duty cycle)		1	V
		(DC-coupled at 20% duty cycle)		2
		(DC-coupled at 10% duty cycle)		2.8
V_IN+/- Current Range⁽³⁾		(AC-coupled)	–50	50	mA peak
V_IN+/- Power		(maintaining common-mode voltage, AC-coupled)		15.3	dBm
V_IN+/- Power		(not maintaining common-mode voltage, AC-coupled)		17.1	dBm
Ground Difference max(GND_TC/DR/E) -min(GND_TC/DR/E)			0		V
CLK+/- Voltage Range			0	V_A	V
Differential CLK Amplitude			0.4	2	V_P-P
V_CMI Common Mode Input Voltage			V_CMO – 150	V_CMO +150	mV

(1) All voltages are measured with respect to GND = GNDTC = GNDDR = GNDE = 0 V, unless otherwise specified.

(2) Proper common mode voltage must be maintained to ensure proper output codes, especially during input overdrive.

(3) This rating is intended for DC-coupled applications; the voltages listed may be safely applied to VIN+/- for the life-time duty-cycle of the part.

(4) Applies only to maximum operating speed.

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		ADC12D1000, ADC12D1600	UNIT
		NXA (BGA)
		292 PINS
R_θJA	Junction-to-ambient thermal resistance	16	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	2.9	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	2.5	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics: Static Converter

Unless otherwise specified, the following apply after calibration for V_A = V_DR = V_TC = V_E = 1.9 V; I- and Q-channels, AC-coupled, unused channel terminated to AC ground, FSR Pin = High; C_L = 10 pF; Differential, AC coupled Sine Wave Sampling Clock, f_CLK = 1 or 1.6 GHz at 0.5 V_P-P with 50% duty cycle (as specified); V_BG = Floating; Non-Extended Control Mode; Rext = Rtrim = 3300 Ω ± 0.1%; Analog Signal Source Impedance = 100-Ω Differential; 1:2 Demultiplex Non-DES Mode; Duty Cycle Stabilizer on. All other limits T_A = 25°C, unless otherwise noted.⁽¹⁾⁽²⁾⁽³⁾

PARAMETER		TEST CONDITIONS		TYP	MAX	UNIT
	Resolution with No Missing Codes	T_A = T_MIN to T_MAX			12	bits
INL	Integral Non-Linearity (Best fit)	1-MHz DC-coupled over-ranged sine wave	T_A = 25°C	±2.5		LSB
INL	Integral Non-Linearity (Best fit)	1-MHz DC-coupled over-ranged sine wave	T_A = T_MIN to T_MAX		±4.8	LSB
DNL	Differential Non-Linearity	1-MHz DC-coupled over-ranged sine wave	T_A = 25°C	±0.4		LSB
DNL	Differential Non-Linearity	1-MHz DC-coupled over-ranged sine wave	T_A = T_MIN to T_MAX		±0.9	LSB
V_OFF	Offset Error			5		LSB
V_OFF_ADJ	Input Offset Adjustment Range	Extended Control Mode		±45		mV
PFSE	Positive Full-Scale Error	See⁽⁴⁾. T_A = T_MIN to T_MAX			±25	mV
NFSE	Negative Full-Scale Error	See⁽⁴⁾. T_A = T_MIN to T_MAX			±25	mV
	Out-of-Range Output Code⁽⁵⁾	(V_IN+) − (V_IN−) > + Full Scale, T_A = T_MIN to T_MAX			4095
	Out-of-Range Output Code⁽⁵⁾	(V_IN+) − (V_IN−) < − Full Scale, T_A = T_MIN to T_MAX			0

(1) The analog inputs, labeled "I/O", are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device). See the following figure. ADC12D1000 ADC12D1600 30091604.gif

(2) To ensure accuracy, it is required that VA, VTC, VE and VDR be well-bypassed. Each supply pin must be decoupled with separate bypass capacitors.

(3) Typical figures are at TA = 25°C, and represent most likely parametric norms. Test limits are ensured to TI's AOQL (Average Outgoing Quality Level).

(4) Calculation of Full-Scale Error for this device assumes that the actual reference voltage is exactly its nominal value. Full-Scale Error for this device, therefore, is a combination of Full-Scale Error and Reference Voltage Error. See Figure 8. For relationship between Gain Error and Full-Scale Error, see Specification Definitions for Gain Error.

(5) This parameter is specified by design and is not tested in production.

6.6 Electrical Characteristics: Dynamic Converter

T_A = 25°C, unless otherwise noted

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
FPBW	Full Power Bandwidth	Non-DES Mode			2.8		GHz
		DESI, DESQ Mode			1.25		GHz
		DESIQ Mode			1.75		GHz
	Gain Flatness	NON-DES MODE
		D.C. to Fs/2	ADC12D1000		0.35		dB
		D.C. to Fs/2	ADC12D1600		0.5		dB
		D.C. to Fs	ADC12D1000		0.5		dB
		D.C. to Fs	ADC12D1600		1		dB
		DESI, DESQ MODE
		D.C. to Fs/2	ADC12D1000		2.4		dB
		D.C. to Fs/2	ADC12D1600		4		dB
		DESIQ MODE
		D.C. to Fs/2	ADC12D1000		1.9		dB
		D.C. to Fs/2	ADC12D1600		2		dB
CER	Code Error Rate				10^–18		Error/Sample
NPR	Noise Power Ratio	See⁽¹⁾	ADC12D1000		49.5		dB
NPR	Noise Power Ratio	See⁽¹⁾	ADC12D1600		48.5		dB
IMD3	3rd order Intermodulation Distortion	F_IN1 = 1212.52 MHz at -7dBFS	ADC12D1000		–66		dBFS
		F_IN1 = 1212.52 MHz at -7dBFS	ADC12D1600		–63		dBFS
		F_IN2 = 1217.52 MHz at -7dBFS DESIQ Mode	ADC12D1000		–59		dBc
		F_IN2 = 1217.52 MHz at -7dBFS DESIQ Mode	ADC12D1600		–56		dBc
	Noise Floor Density	50Ω single-ended termination, DES Mode	ADC12D1000		–152.6		dBm/Hz
			ADC12D1600		–153.6		dBm/Hz
			ADC12D1000		–151.6		dBFS/Hz
			ADC12D1600		–152.6		dBFS/Hz
		Wideband input, DES Mode⁽²⁾	ADC12D1000		–151.5		dBm/Hz
			ADC12D1600		–152.6		dBm/Hz
			ADC12D1000		–150.5		dBFS/Hz
			ADC12D1600		–151.6		dBFS/Hz
NON-DES MODE⁽²⁾⁽²⁾
ENOB	Effective Number of Bits	A_IN = 125 MHz at –0.5 dBFS	ADC12D1000		9.6		bits
		A_IN = 125 MHz at –0.5 dBFS	ADC12D1600		9.4		bits
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1000 T_A = T_MIN to T_MAX	9.5 8.7			bits
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1600 T_A = T_MIN to T_MAX	9.4 8.6			bits
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1000 T_A = T_MIN to T_MAX	9.4 8.7			bits
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1600 T_A = T_MIN to T_MAX	9.3 8.6			bits
		A_IN = 998 MHz at –0.5 dBFS			8.9		bits
		A_IN = 1448 MHz at –0.5 dBFS			8.6		bits
SINAD	Signal-to-Noise Plus Distortion Ratio	A_IN = 125 MHz at –0.5 dBFS	ADC12D1000		59.7		dB
		A_IN = 125 MHz at –0.5 dBFS	ADC12D1600		58.2		dB
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1000 T_A = T_MIN to T_MAX	59 54.1			dB
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1600 T_A = T_MIN to T_MAX	58 53.5			dB
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1000 T_A = T_MIN to T_MAX	58.2 54.1			dB
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1600 T_A = T_MIN to T_MAX	57.8 53.5			dB
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1000		55.4		dB
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1600		55.1		dB
		A_IN = 1448 MHz at –0.5 dBFS	ADC12D1000		53.6		dB
		A_IN = 1448 MHz at –0.5 dBFS	ADC12D1600		53.8		dB
SNR	Signal-to-Noise Ratio	A_IN = 125 MHz at –0.5 dBFS	ADC12D1000		60.2		dB
		A_IN = 125 MHz at –0.5 dBFS	ADC12D1600		58.5		dB
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1000 T_A = T_MIN to T_MAX	59.7 55.1			dB
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1600 T_A = T_MIN to T_MAX	58.7 54.6			dB
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1000 T_A = T_MIN to T_MAX	58.7 55.1			dB
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1600 T_A = T_MIN to T_MAX	58.5 54.6			dB
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1000		56.3		dB
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1600		56.5		dB
		A_IN = 1448 MHz at –0.5 dBFS	ADC12D1000		54.1		dB
		A_IN = 1448 MHz at –0.5 dBFS	ADC12D1600		55		dB
THD	Total Harmonic Distortion	A_IN = 125 MHz at –0.5 dBFS	ADC12D1000		–68.7		dB
		A_IN = 125 MHz at –0.5 dBFS	ADC12D1600		–70.3		dB
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1000 T_A = T_MIN to T_MAX			–67 –61	dB
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1600 T_A = T_MIN to T_MAX			–66.6 –60	dB
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1000 T_A = T_MIN to T_MAX			–67.4 –61	dB
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1600 T_A = T_MIN to T_MAX			–66 –60	dB
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1000		–62.9		dB
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1600		–60.8		dB
		A_IN = 1448 MHz at –0.5 dBFS	ADC12D1000		–63		dB
		A_IN = 1448 MHz at –0.5 dBFS	ADC12D1600		–60		dB
2nd Harm	Second Harmonic Distortion	A_IN = 125 MHz at –0.5 dBFS	ADC12D1000		–75.7		dBc
		A_IN = 125 MHz at –0.5 dBFS	ADC12D1600		–75		dBc
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1000		–75.7		dBc
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1600		–80		dBc
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1000		–79.8		dBc
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1600		–71		dBc
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1000		–70		dBc
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1600		–73		dBc
		A_IN = 1448 MHz at –0.5 dBFS			–67		dBc
3rd Harm	Third Harmonic Distortion	A_IN = 125 MHz at –0.5 dBFS	ADC12D1000		–71		dBc
		A_IN = 125 MHz at –0.5 dBFS	ADC12D1600		–74		dBc
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1000		–68.4		dBc
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1600		–68		dBc
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1000		–68.7		dBc
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1600		–69		dBc
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1000		–66		dBc
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1600		–62		dBc
		A_IN = 1448 MHz at –0.5 dBFS	ADC12D1000		–67		dBc
		A_IN = 1448 MHz at –0.5 dBFS	ADC12D1600		–61		dBc
SFDR	Spurious-Free Dynamic Range	A_IN = 125 MHz at –0.5 dBFS	ADC12D1000		71		dBc
		A_IN = 125 MHz at –0.5 dBFS	ADC12D1600		70.3		dBc
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1000 T_A = T_MIN to T_MAX	68.4 61			dBc
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1600 T_A = T_MIN to T_MAX	68 60			dBc
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1000 T_A = T_MIN to T_MAX	68.7 61			dBc (min)
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1600 T_A = T_MIN to T_MAX	68.2 60			dBc (min)
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1000		66		dBc
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1600		62		dBc
		A_IN = 1448 MHz at –0.5 dBFS	ADC12D1000		67		dBc
		A_IN = 1448 MHz at –0.5 dBFS	ADC12D1600		61.9		dBc
DES MODE⁽²⁾⁽²⁾⁽²⁾
ENOB	Effective Number of Bits	A_IN = 125 MHz at –0.5 dBFS	ADC12D1000		9.5		bits
		A_IN = 125 MHz at –0.5 dBFS	ADC12D1600		9.4		bits
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1000 T_A = T_MIN to T_MAX	9.4 8.7			bits
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1600 T_A = T_MIN to T_MAX	9.2 8.6			bits
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1000		9.2		bits
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1600		9.1		bits
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1000		8.8		bits
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1600		8.5		bits
		A_IN = 1448 MHz at –0.5 dBFS	ADC12D1000		8.6		bits
		A_IN = 1448 MHz at –0.5 dBFS	ADC12D1600		8.5		bits
SINAD	Signal-to-Noise Plus Distortion Ratio	A_IN = 125 MHz at –0.5 dBFS	ADC12D1000		59		dB
		A_IN = 125 MHz at –0.5 dBFS	ADC12D1600		58.2		dB
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1000 T_A = T_MIN to T_MAX	58.6 54			dB
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1600 T_A = T_MIN to T_MAX	57 53.5			dB
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1000		57.3		dB
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1600		56.9		dB
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1000		54.5		dB
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1600		52.7		dB
		A_IN = 1448 MHz at –0.5 dBFS	ADC12D1000		53.9		dB
		A_IN = 1448 MHz at –0.5 dBFS	ADC12D1600		52.7		dB
SNR	Signal-to-Noise Ratio	A_IN = 125 MHz at –0.5 dBFS	ADC12D1000		59.2		dB
		A_IN = 125 MHz at –0.5 dBFS	ADC12D1600		58.6		dB
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1000 T_A = T_MIN to T_MAX	58.9 55.3			dB
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1600 T_A = T_MIN to T_MAX	57.9 54.6			dB
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1000		58.3		dB
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1600		57.6		dB
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1000		55.9		dB
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1600		53.6		dB
		A_IN = 1448 MHz at –0.5 dBFS	ADC12D1000		54.2		dB
		A_IN = 1448 MHz at –0.5 dBFS	ADC12D1600		53.3		dB
THD	Total Harmonic Distortion	A_IN = 125 MHz at –0.5 dBFS	ADC12D1000		–74		dB
		A_IN = 125 MHz at –0.5 dBFS	ADC12D1600		–68.2		dB
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1000 T_A = T_MIN to T_MAX			–71.2 –60	dB
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1600 T_A = T_MIN to T_MAX			–64.6 –60	dB
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1000		–63.8		dB
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1600		–66.3		dB
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1000		–60		dB
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1600		–60		dB
		A_IN = 1448 MHz at –0.5 dBFS	ADC12D1000		–65		dB
		A_IN = 1448 MHz at –0.5 dBFS	ADC12D1600		–61.7		dB
2nd Harm	Second Harmonic Distortion	A_IN = 125 MHz at –0.5 dBFS	ADC12D1000		–82		dBc
		A_IN = 125 MHz at –0.5 dBFS	ADC12D1600		–77.3		dBc
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1000		–82		dBc
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1600		–82.7		dBc
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1000		–72		dBc
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1600		–71.6		dBc
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1000		–63.2		dBc
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1600		–63		dBc
		A_IN = 1448 MHz at –0.5 dBFS	ADC12D1000		–75		dBc
		A_IN = 1448 MHz at –0.5 dBFS	ADC12D1600		–75.6		dBc
3rd Harm	Third Harmonic Distortion	A_IN = 125 MHz at –0.5 dBFS	ADC12D1000		–82		dBc
		A_IN = 125 MHz at –0.5 dBFS	ADC12D1600		–69.8		dBc
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1000		–73		dBc
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1600		–65.3		dBc
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1000		–65		dBc
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1600		–67.3		dBc
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1000		–65		dBc
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1600		–63		dBc
		A_IN = 1448 MHz at –0.5 dBFS	ADC12D1000		–67		dBc
		A_IN = 1448 MHz at –0.5 dBFS	ADC12D1600		–62.4		dBc
SFDR	Spurious-Free Dynamic Range	A_IN = 125 MHz at –0.5 dBFS	ADC12D1000		69		dBc
		A_IN = 125 MHz at –0.5 dBFS	ADC12D1600		69.8		dBc
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1000 T_A = T_MIN to T_MAX	69 60			dBc
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1600 T_A = T_MIN to T_MAX	65.3 60			dBc
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1000		65		dBc
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1600		67.3		dBc
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1000		64		dBc
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1600		60.2		dBc
		A_IN = 1448 MHz at –0.5 dBFS	ADC12D1000		66		dBc
		A_IN = 1448 MHz at –0.5 dBFS	ADC12D1600		60		dBc

(1) The NPR was measured using an Agilent N6030A Arbitrary Waveform Generator (ARB) to generate the input signal. See the Wideband Performance for an example spectrum. The "noise" portion of the signal was created by tones spaced at 500 kHz and the "notch" was a 25-MHz absence of tones centered at 320 MHz. The bandwidth of this equipment is only 500 MHz, so the final reported NPR was extrapolated from the measured NPR as if the entire Nyquist band were occupied with noise.

(2) The Noise Floor was measured for two conditions: the analog input terminated with 50 Ω, and in the presence of a 500-MHz wideband noise signal with total power just below the maximum input level to the ADC. In both cases, the spurs at DC, Fs/4 and Fs/2 were removed. The power over the entire Nyquist band (except the noise signal) was integrated and the average number is reported.

6.7 Electrical Characteristics: Analog Input/Output and Reference

T_A = 25°C, unless otherwise noted

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
ANALOG INPUTS
V_{IN_FSR}	Analog Differential Input Full Scale Range	NON-EXTENDED CONTROL MODE
		FSR Pin Low	ADC12D1000 T_A = T_MIN to T_MAX	540	600	660	mV_P-P
		FSR Pin Low	ADC12D1600 T_A = T_MIN to T_MAX	540	600	660	mV_P-P
		FSR Pin High	ADC12D1000 T_A = T_MIN to T_MAX	740	800	860	mV_P-P
		FSR Pin High	ADC12D1600 T_A = T_MIN to T_MAX	740	800	860	mV_P-P
		EXTENDED CONTROL MODE
		FM(14:0) = 0000h			600		mV_P-P
		FM(14:0) = 4000h (default)			800		mV_P-P
		FM(14:0) = 7FFFh			1000		mV_P-P
C_IN	Analog Input Capacitance, Non-DES Mode⁽¹⁾⁽²⁾	Differential			0.02		pF
	Analog Input Capacitance, Non-DES Mode⁽¹⁾⁽²⁾	Each input pin to ground			1.6		pF
	Analog Input Capacitance, DES Mode⁽¹⁾⁽²⁾	Differential			0.08		pF
	Analog Input Capacitance, DES Mode⁽¹⁾⁽²⁾	Each input pin to ground			2.2		pF
R_IN	Differential Input Resistance	ADC12D1000 T_A = T_MIN to T_MAX		91	100	109	Ω
R_IN	Differential Input Resistance	ADC12D1600 T_A = T_MIN to T_MAX		91	100	109	Ω
COMMON-MODE OUTPUT
V_CMO	Common-Mode Output Voltage	I_CMO = ±100 µA	ADC12D1000 T_A = T_MIN to T_MAX	1.15	1.25	1.35	V
V_CMO	Common-Mode Output Voltage	I_CMO = ±100 µA	ADC12D1600 T_A = T_MIN to T_MAX	1.15	1.25	1.35	V
TC_V_CMO	Common-Mode Output Voltage Temperature Coefficient	I_CMO = ±100 µA			38		ppm/°C
V_{CMO_LVL}	V_CMO input threshold to set DC-coupling Mode				0.63		V
C_L_V_CMO	Maximum V_CMO Load Capacitance	See⁽¹⁾				80	pF
BANDGAP REFERENCE
V_BG	Bandgap Reference Output Voltage	I_BG = ±100 µA	ADC12D1000 T_A = T_MIN to T_MAX	1.15	1.25	1.35	V
V_BG	Bandgap Reference Output Voltage	I_BG = ±100 µA	ADC12D1600 T_A = T_MIN to T_MAX	1.15	1.25	1.35	V
TC_V_BG	Bandgap Reference Voltage Temperature Coefficient	I_BG = ±100 µA			32		ppm/°C
C_L_V_BG	Maximum Bandgap Reference load Capacitance	See⁽¹⁾				80	pF

(1) This parameter is specified by design and is not tested in production.

(2) The differential and pin-to-ground input capacitances are lumped capacitance values from design; they are defined as shown below ADC12D1000 ADC12D1600 30091636.gif

6.8 Electrical Characteristics: I-Channel To Q-Channel

PARAMETER		TEST CONDITIONS	TYP	UNIT
	Offset Match		2	LSB
	Positive Full-Scale Match	Zero offset selected in Control Register	2	LSB
	Negative Full-Scale Match	Zero offset selected in Control Register	2	LSB
	Phase Matching (I, Q)	f_IN = 1 GHz	< 1	Degree
X-TALK	Crosstalk from I-channel (Aggressor) to Q-channel (Victim)	Aggressor = 867 MHz F.S. Victim = 100 MHz F.S.	−70	dB
X-TALK	Crosstalk from Q-channel (Aggressor) to I-channel (Victim)	Aggressor = 867 MHz F.S. Victim = 100 MHz F.S.	−70	dB

6.9 Electrical Characteristics: Converter and Sampling Clock

T_A = 25°C, unless otherwise noted

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
V_{IN_CLK}	Differential Sampling Clock Input Level⁽²⁾	Sine Wave Clock Differential Peak-to-Peak	ADC12D1000 T_A = T_MIN to T_MAX	0.4	0.6	2	V_P-P
		Sine Wave Clock Differential Peak-to-Peak	ADC12D1600 T_A = T_MIN to T_MAX	0.4	0.6	2	V_P-P
		Square Wave Clock Differential Peak-to-Peak	ADC12D1000 T_A = T_MIN to T_MAX	0.4	0.6	2	V_P-P (min)
		Square Wave Clock Differential Peak-to-Peak	ADC12D1600 T_A = T_MIN to T_MAX	0.4	0.6	2	V_P-P (max)
C_{IN_CLK}	Sampling Clock Input Capacitance⁽¹⁾	Differential			0.1		pF
C_{IN_CLK}	Sampling Clock Input Capacitance⁽¹⁾	Each input to ground			1		pF
R_{IN_CLK}	Sampling Clock Differential Input Resistance				100		Ω

6.10 Electrical Characteristics: Autosync Feature

PARAMETER		TEST CONDITIONS	TYP	UNIT
V_{IN_RCLK}	Differential RCLK Input Level	Differential Peak-to-Peak	360	mV_P-P
C_{IN_RCLK}	RCLK Input Capacitance	Differential	0.1	pF
C_{IN_RCLK}	RCLK Input Capacitance	Each input to ground	1	pF
R_{IN_RCLK}	RCLK Differential Input Resistance		100	Ω
I_{IH_RCLK}	Input Leakage Current; V_IN = V_A		22	µA
I_{IL_RCLK}	Input Leakage Current; V_IN = GND		–33	µA
V_{O_RCOUT}	Differential RCOut Output Voltage		360	mV

6.11 Electrical Characteristics: Digital Control and Output Pin

T_A = 25°C, unless otherwise noted

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
DIGITAL CONTROL PINS (DES, CalDly, CAL, PDI, PDQ, TPM, NDM, FSR, DDRPh, ECE, SCLK, SDI, SCS)
V_IH	Logic High Input Voltage	T_A = T_MIN to T_MAX		0.7×V_A			V
V_IL	Logic Low Input Voltage	T_A = T_MIN to T_MAX				0.3×V_A	V
I_IH	Input Leakage Current; V_IN = V_A				0.02		μA
I_IL	Input Leakage Current; V_IN = GND	FSR, CalDly, CAL, NDM, TPM, DDRPh, DES			–0.02		μA
		SCS, SCLK, SDI			–17		μA
		PDI, PDQ, ECE			–38		μA
C_{IN_DIG}	Digital Control Pin Input Capacitance⁽¹⁾	Measured from each control pin to GND			1.5		pF
DIGITAL OUTPUT PINS (DATA, DCLKI, DCLKQ, ORI, ORQ)
V_OD	LVDS Differential Output Voltage	V_BG = Floating, OVS = High	ADC12D1000 T_A = T_MIN to T_MAX	400	630	800	mV_P-P
		V_BG = Floating, OVS = High	ADC12D1600 T_A = T_MIN to T_MAX	400	630	800	mV_P-P
		V_BG = Floating, OVS = Low	ADC12D1000 T_A = T_MIN to T_MAX	230	460	630	mV_P-P
		V_BG = Floating, OVS = Low	ADC12D1600 T_A = T_MIN to T_MAX	230	460	630	mV_P-P
		V_BG = V_A, OVS = High			670		mV_P-P
		V_BG = V_A, OVS = Low			500		mV_P-P
ΔV_{O DIFF}	Change in LVDS Output Swing Between Logic Levels				±1		mV
V_OS	Output Offset Voltage	V_BG = Floating			0.8		V
V_OS	Output Offset Voltage	V_BG = V_A			1.2		V
ΔV_OS	Output Offset Voltage Change Between Logic Levels				±1		mV
I_OS	Output Short-Circuit Current	V_BG = Floating; D+ and D− connected to 0.8 V			±4		mA
Z_O	Differential Output Impedance				100		Ω
V_OH	Logic High-Output Level	CalRun, I_OH = −100 µA⁽²⁾, SDO, I_OH = −400 µA⁽²⁾			1.65		V
V_OL	Logic Low Output Level	CalRun, I_OL = 100 µA⁽²⁾, SDO, I_OL = 400 µA⁽²⁾			0.15		V
DIFFERENTIAL DCLK RESET PINS (DCLK_RST)
V_{CMI_DRST}	DCLK_RST Common-Mode Input Voltage				1.25		V
V_{ID_DRST}	Differential DCLK_RST Input Voltage				V_{IN_CLK}		V_P-P
R_{IN_DRST}	Differential DCLK_RST Input Resistance	See⁽¹⁾			100		Ω

6.12 Electrical Characteristics: Power Supply

T_A = 25°C, unless otherwise noted

PARAMETER		TEST CONDITIONS		TYP	MAX	UNIT
I_A	Analog Supply Current	PDI = PDQ = Low	ADC12D1000	1110		mA
		PDI = PDQ = Low	ADC12D1600	1235		mA
		PDI = Low; PDQ = High	ADC12D1000	610		mA
		PDI = Low; PDQ = High	ADC12D1600	670		mA
		PDI = High; PDQ = Low	ADC12D1000	610		mA
		PDI = High; PDQ = Low	ADC12D1600	670		mA
		PDI = PDQ = High		15		mA
I_TC	Track-and-Hold and Clock Supply Current	PDI = PDQ = Low	ADC12D1000	400		mA
		PDI = PDQ = Low	ADC12D1600	470		mA
		PDI = Low; PDQ = High	ADC12D1000	240		mA
		PDI = Low; PDQ = High	ADC12D1600	280		mA
		PDI = High; PDQ = Low	ADC12D1000	240		mA
		PDI = High; PDQ = Low	ADC12D1600	280		mA
		PDI = PDQ = High		4		mA
I_DR	Output Driver Supply Current	PDI = PDQ = Low	ADC12D1000	305		mA
		PDI = PDQ = Low	ADC12D1600	325		mA
		PDI = Low; PDQ = High	ADC12D1000	160		mA
		PDI = Low; PDQ = High	ADC12D1600	170		mA
		PDI = High; PDQ = Low	ADC12D1000	160		mA
		PDI = High; PDQ = Low	ADC12D1600	170		mA
		PDI = PDQ = High		3		mA
I_E	Digital Encoder Supply Current	PDI = PDQ = Low	ADC12D1000	80		mA
		PDI = PDQ = Low	ADC12D1600	140		mA
		PDI = Low; PDQ = High	ADC12D1000	40		mA
		PDI = Low; PDQ = High	ADC12D1600	70		mA
		PDI = High; PDQ = Low	ADC12D1000	40		mA
		PDI = High; PDQ = Low	ADC12D1600	70		mA
		PDI = PDQ = High		1		mA
I_TOTAL	Total Supply Current	1:2 Demux Mode PDI = PDQ = Low	ADC12D1000 T_A = T_MIN to T_MAX	1895	2105	mA
		1:2 Demux Mode PDI = PDQ = Low	ADC12D1600 T_A = T_MIN to T_MAX	2170	2310	mA
		Non-Demux Mode PDI = PDQ = Low	ADC12D1000	1780		mA
		Non-Demux Mode PDI = PDQ = Low	ADC12D1600	2040		mA
P_C	Power Consumption	1:2 Demux Mode
		PDI = PDQ = Low	ADC12D1000 T_A = T_MIN to T_MAX	3.60	4	W
		PDI = PDQ = Low	ADC12D1600 T_A = T_MIN to T_MAX	4.12	4.4	W
		PDI = Low; PDQ = High	ADC12D1000	1.99		W
		PDI = Low; PDQ = High	ADC12D1600	2.26		W
		PDI = High; PDQ = Low	ADC12D1000	1.99		W
		PDI = High; PDQ = Low	ADC12D1600	2.26		W
		PDI = PDQ = High		43		mW
		Non-Demux Mode PDI = PDQ = Low	ADC12D1000	3.38		W
		Non-Demux Mode PDI = PDQ = Low	ADC12D1600	3.88		W

6.13 Electrical Characteristics: AC

T_A = 25°C, unless otherwise noted

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
SAMPLING CLOCK (CLK)
f_{CLK (max)}	Maximum Sampling Clock Frequency	ADC12D1000 T_A = T_MIN to T_MAX				1.0	GHz
f_{CLK (max)}	Maximum Sampling Clock Frequency	ADC12D1600 T_A = T_MIN to T_MAX				1.6	GHz
f_{CLK (min)}	Minimum Sampling Clock Frequency	Non-DES Mode; LFS = 0b	ADC12D1000 T_A = T_MIN to T_MAX	300			MHz
		Non-DES Mode; LFS = 0b	ADC12D1600 T_A = T_MIN to T_MAX	300			MHz
		Non-DES Mode; LFS = 1b, T_A = T_MIN to T_MAX		150			MHz
		DES Mode, T_A = T_MIN to T_MAX		500			MHz
	Sampling Clock Duty Cycle	f_CLK(min) ≤ f_CLK ≤ f_CLK(max)⁽²⁾	ADC12D1000 T_A = T_MIN to T_MAX	20%	50%	80%
	Sampling Clock Duty Cycle	f_CLK(min) ≤ f_CLK ≤ f_CLK(max)⁽²⁾	ADC12D1600 T_A = T_MIN to T_MAX	20%	50%	80%
t_CL	Sampling Clock Low Time	See⁽¹⁾	ADC12D1000 T_A = T_MIN to T_MAX	200	500		ps
t_CL	Sampling Clock Low Time	See⁽¹⁾	ADC12D1600 T_A = T_MIN to T_MAX	125	312.5		ps
t_CH	Sampling Clock High Time	See⁽¹⁾	ADC12D1000 T_A = T_MIN to T_MAX	200	500		p
t_CH	Sampling Clock High Time	See⁽¹⁾	ADC12D1600 T_A = T_MIN to T_MAX	125	312.5		p
DATA CLOCK (DCLKI, DCLKQ)
	DCLK Duty Cycle	See⁽¹⁾	ADC12D1000 T_A = T_MIN to T_MAX	45%	50%	55%
	DCLK Duty Cycle	See⁽¹⁾	ADC12D1600 T_A = T_MIN to T_MAX	45%	50%	55%
t_SR	Setup Time DCLK_RST±	See⁽²⁾			45		ps
t_HR	Hold Time DCLK_RST±	See⁽²⁾			45		ps
t_PWR	Pulse Width DCLK_RST±	See⁽¹⁾, T_A = T_MIN to T_MAX		5			Sampling Clock Cycles
t_{SYNC_DLY}	DCLK Synchronization Delay	90° Mode⁽¹⁾, T_A = T_MIN to T_MAX		4			Sampling Clock Cycles
t_{SYNC_DLY}	DCLK Synchronization Delay	0° Mode⁽¹⁾, T_A = T_MIN to T_MAX		5			Sampling Clock Cycles
t_LHT	Differential Low-to-High Transition Time	10%-to-90%, C_L = 2.5 pF			200		ps
t_HLT	Differential High-to-Low Transition Time	10%-to-90%, C_L = 2.5 pF			200		ps
t_SU	Data-to-DCLK Setup Time	90° Mode⁽¹⁾	ADC12D1000		870		ps
t_SU	Data-to-DCLK Setup Time	90° Mode⁽¹⁾	ADC12D1600		500		ps
t_H	DCLK-to-Data Hold Time	90° Mode⁽¹⁾	ADC12D1000		870		ps
t_H	DCLK-to-Data Hold Time	90° Mode⁽¹⁾	ADC12D1600		500		ps
t_OSK	DCLK-to-Data Output Skew	50% of DCLK transition to 50% of Data transition⁽¹⁾				±50	ps
DATA INPUT-TO-OUTPUT
t_AD	Aperture Delay	Sampling CLK+ Rise to Acquisition of Data			1.15		ns
t_AJ	Aperture Jitter				0.2		ps (rms)
t_OD	Sampling Clock-to Data Output Delay (in addition to Latency)	50% of Sampling Clock transition to 50% of Data transition			3.2		ns
t_LAT	Latency in 1:2 Demux Non-DES Mode⁽¹⁾	DI, DQ Outputs, T_A = T_MIN to T_MAX				34	Sampling Clock Cycles
	Latency in 1:2 Demux Non-DES Mode⁽¹⁾	DId, DQd Outputs, T_A = T_MIN to T_MAX				35
	Latency in 1:4 Demux DES Mode⁽¹⁾	DI Outputs, T_A = T_MIN to T_MAX				34
		DQ Outputs, T_A = T_MIN to T_MAX				34.5
		DId Outputs, T_A = T_MIN to T_MAX				35
		DQd Outputs, T_A = T_MIN to T_MAX				35.5
	Latency in Non-Demux Non-DES Mode⁽¹⁾	DI Outputs, T_A = T_MIN to T_MAX				34
	Latency in Non-Demux Non-DES Mode⁽¹⁾	DQ Outputs, T_A = T_MIN to T_MAX				34
	Latency in Non-Demux DES Mode⁽¹⁾	DI Outputs, T_A = T_MIN to T_MAX				34
	Latency in Non-Demux DES Mode⁽¹⁾	DQ Outputs, T_A = T_MIN to T_MAX				34.5
t_ORR	Over-Range Recovery Time	Differential V_IN step from ±1.2 V to 0 V to accurate conversion			1		Sampling Clock Cycle
t_WU	Wake-Up Time (PDI/PDQ low to Rated Accuracy Conversion)	Non-DES Mode⁽¹⁾			500		ns
t_WU	Wake-Up Time (PDI/PDQ low to Rated Accuracy Conversion)	DES Mode⁽¹⁾			1		µs

6.14 Timing Requirements: Serial Port Interface

T_A = 25°C, unless otherwise noted

			MIN	TYP	UNIT
f_SCLK	Serial Clock Frequency	See⁽¹⁾		15	MHz
	Serial Clock Low Time	T_A = T_MIN to T_MAX	30		ns
	Serial Clock High Time	T_A = T_MIN to T_MAX	30		ns
t_SSU	Serial Data-to-Serial Clock Rising Setup Time	See⁽¹⁾	2.5		ns
t_SH	Serial Data-to-Serial Clock Rising Hold Time	See⁽¹⁾	1		ns
t_SCS	SCS-to-Serial Clock Rising Setup Time			2.5	ns
t_HCS	SCS-to-Serial Clock Falling Hold Time			1.5	ns
t_BSU	Bus turnaround time			10	ns

6.15 Timing Requirements: Calibration

T_A = 25°C, unless otherwise noted

			MIN	TYP	MAX	UNIT
t_CAL	Calibration Cycle Time	CSS = 0b		5.2·10⁷		Sampling Clock Cycles
t_CAL	Calibration Cycle Time	CSS = 1b		5.2·10⁷		Sampling Clock Cycles
t_{CAL_L}	CAL Pin Low Time	See⁽¹⁾, T_A = T_MIN to T_MAX	1280			Sampling Clock Cycles
t_{CAL_H}	CAL Pin High Time	See⁽¹⁾, T_A = T_MIN to T_MAX	1280			Sampling Clock Cycles
t_CalDly	Calibration delay determined by CalDly Pin⁽¹⁾	CalDly = Low, T_A = T_MIN to T_MAX			2²⁴	Sampling Clock Cycles
t_CalDly	Calibration delay determined by CalDly Pin⁽¹⁾	CalDly = High, T_A = T_MIN to T_MAX			2³⁰	Sampling Clock Cycles

(1) This parameter is specified by design and is not tested in production.

(2) This parameter is specified by design and/or characterization and is not tested in production.

(3) Proper common mode voltage must be maintained to ensure proper output codes, especially during input overdrive.

The timing for these figures is shown for the one input only (I or Q). However, both I- and Q-inputs may be used. For this case, the I-channel functions precisely the same as the Q-channel, with VinI, DCLKI, DId and DI instead of VinQ, DCLKQ, DQd and DQ. Both I- and Q-channel use the same CLK.

Figure 1. Clocking in 1:2 Demux Non-DES Mode*

Figure 2. Clocking in Non-Demux Non-DES Mode*

Figure 3. Clocking in 1:4 Demux DES Mode*

Figure 4. Clocking in Non-Demux Mode DES Mode*

Figure 5. Data Clock Reset Timing (Demux Mode)

Figure 6. Power-on and On-Command Calibration Timing

Figure 7. Serial Interface Timing

Figure 8. Input / Output Transfer Characteristic

6.16 Typical Characteristics

V_A= V_DR = V_TC = V_E = 1.9 V, f_CLK = 1.0/1.6 GHz, f_IN = 498 MHz, T_A= 25°C, I-channel, 1:2 Demux Non-DES Mode (1:1 Demux Non-DES Mode has similar performance), unless otherwise stated. For NPR plots, notch width = 25 MHz, fc = 320 MHz.

Figure 9. INL vs Code (ADC12D1000)

Figure 11. INL vs Temperature (ADC12D1000)

Figure 13. DNL vs Code (ADC12D1000)

Figure 15. DNL vs Temperature (ADC12D1000)

Figure 17. ENOB vs Temperature (ADC12D1000)

Figure 19. ENOB vs Supply Voltage (ADC12D1000)

Figure 21. ENOB vs Clock Frequency (ADC12D1000)

Figure 23. ENOB vs Input Frequency (ADC12D1000)

Figure 25. ENOB vs V_CMI (ADC12D1000)

Figure 27. SNR vs Temperature (ADC12D1000)

Figure 29. SNR vs Supply Voltage (ADC12D1000)

Figure 31. SNR vs Clock Frequency (ADC12D1000)

Figure 33. SNR vs Input Frequency (ADC12D1000)

Figure 35. THD vs Temperature (ADC12D1000)

Figure 37. THD vs Supply Voltage (ADC12D1000)

Figure 39. THD vs Clock Frequency (ADC12D1000)

Figure 41. THD vs Input Frequency (ADC12D1000)

Figure 43. SFDR vs Temperature (ADC12D1000)

Figure 45. SFDR vs Supply Voltage (ADC12D1000)

Figure 47. SFDR vs Clock Frequency (ADC12D1000)

Figure 49. SFDR vs Input Frequency (ADC12D1000)

Figure 51. Spectral Response at FIN = 498 MHz (ADC12D1000)

Figure 53. Spectral Response at FIN = 498 MHz (ADC12D1000)

Figure 55. Crosstalk vs Source Frequency (ADC12D1000)

Figure 57. Full Power Bandwidth (ADC12D1000)

Figure 59. Power Consumption vs Clock Frequency (ADC12D1000)

Figure 61. NPR vs RMS Noise Loading Level (ADC12D1000)

Figure 10. INL vs Code (ADC12D1600)

Figure 12. INL vs Temperature (ADC12D1600)

Figure 14. DNL vs Code (ADC12D1600)

Figure 16. DNL vs Temperature (ADC12D1600)

Figure 18. ENOB vs Temperature (ADC12D1600)

Figure 20. ENOB vs Supply Voltage (ADC12D1600)

Figure 22. ENOB vs Clock Frequency (ADC12D1600)

Figure 24. ENOB vs Input Frequency (ADC12D1600)

Figure 26. ENOB vs V_CMI (ADC12D1600)

Figure 28. SNR vs Temperature (ADC12D1600)

Figure 30. SNR vs Supply Voltage (ADC12D1600)

Figure 32. SNR vs Clock Frequency (ADC12D1600)

Figure 34. SNR vs Input Frequency (ADC12D1600)

Figure 36. THD vs Temperature (ADC12D1600)

Figure 38. THD vs Supply Voltage (ADC12D1600)

Figure 40. THD vs Clock Frequency (ADC12D1600)

Figure 42. THD vs Input Frequency (ADC12D1600)

Figure 44. SFDR vs Temperature (ADC12D1600)

Figure 46. SFDR vs Supply Voltage (ADC12D1600)

Figure 48. SFDR vs Clock Frequency (ADC12D1600)

Figure 50. SFDR vs Input Frequency (ADC12D1600)

Figure 52. Spectral Response at FIN = 498 MHz (ADC12D1600)

Figure 54. Spectral Response at FIN = 498 MHz (ADC12D1600)

Figure 56. Crosstalk vs Source Frequency (ADC12D1600)

Figure 58. Full Power Bandwidth (ADC12D1600)

Figure 60. Power Consumption vs Clock Frequency (ADC12D1600)

Figure 62. NPR vs RMS Noise Loading Level (ADC12D1600)