High-speed, high-performance ADCs such as the ADC12D1620 require a very stable input clock signal with minimum phase noise or jitter. ADC jitter requirements are defined by the ADC resolution (number of bits), maximum ADC input frequency, and the input signal amplitude relative to the ADC input full-scale range. The maximum jitter (the sum of the jitter from all sources) allowed to prevent a jitter-induced reduction in SNR is found to be:

where

• t_J(MAX) is the rms total of all jitter sources in seconds
• V_IN(P-P) is the peak-to-peak analog input signal
• V_FSR is the full-scale range of the ADC
• N is the ADC resolution in bits
• f_IN is the maximum input frequency, in Hertz, at the ADC analog input

t_J(MAX) is the square root of the sum of the squares (RSS) of the jitter from all sources, including: ADC input clock, system, input signals, and the ADC itself. Because the effective jitter added by the ADC is beyond user control, TI recommends keeping the sum of all other externally added jitter to a minimum.