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ZHCSGI8A April 2017 – October 2021 ADC12D1620QML-SP

PRODUCTION DATA

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请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)

FVA|256
NAA|376

散热焊盘机械数据 (封装 | 引脚)

订购信息

zhcsgi8a_oa

6.13 Converter Electrical Characteristics: AC Electrical Characteristics

The following specifications apply after calibration for V_A = V_DR = V_TC = V_E = 1.9 V; I and Q channels AC-coupled, FSR pin = high; C_L = 10 pF; differential AC-coupled sine wave input clock, f_CLK = 1.6 GHz at 0.5 V_P-P with 50% duty cycle; V_BG = floating; non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2 demultiplex non-DES mode; I and Q channels; duty-cycle stabilizer on.⁽¹⁾⁽²⁾

PARAMETER		CONDITIONS		SUB-GROUPS	MIN	TYP⁽³⁾	MAX	UNIT
INPUT CLOCK (CLK)
f_{CLK (max)}	Maximum input clock frequency	Non-LSPSM		[9, 10, 11]	1.6			GHz
f_{CLK (max)}	Maximum input clock frequency	LSPSM		[9, 10, 11]	800			MHz
f_{CLK (min)}	Minimum input clock frequency	Non-LSPSM	Non-DES mode; LFS = 1b	[9, 10, 11]			200	MHz
		Non-LSPSM	DES mode	[9, 10, 11]			250	MHz
		LSPSM	Non-DES mode	[9, 10, 11]			200	MHz
	Input clock duty cycle⁽⁴⁾	f_CLK(min) ≤ f_CLK ≤ f_CLK (max)			20%	50%	80%
t_CL	Input clock low time⁽⁴⁾				200	500		ps
t_CH	Input clock high time⁽⁴⁾				200	500		ps
DCLK_RST
t_SR	Setup time DCLK_RST±					45		ps
t_HR	Hold time DCLK_RST±					45		ps
t_PWR	Pulse width DCLK_RST±					5		Input Clock Cycles
DATA CLOCK (DCLKI, DCLKQ)
	DCLK duty cycle					50%
t_{SYNC_DLY}	DCLK synchronization delay	90° mode				4		Input Clock Cycles
t_{SYNC_DLY}	DCLK synchronization delay	0° mode				5		Input Clock Cycles
t_LHT	Differential low-to-high transition time	10% to 90%, C_L = 2.5-pF				200		ps
t_HLT	Differential high-to-low transition time	10% to 90%, C_L = 2.5-pF				200		ps
t_SU	Data-to-DCLK set-up time	DDR mode, 90° DCLK				500		ps
t_H	DCLK-to-data hold time	DDR mode, 90° DCLK				500		ps
t_OSK	DCLK-to-data output skew	50% of DCLK transition to 50% of data transition				±50		ps
DATA INPUT-TO-OUTPUT
t_AD	Sampling (aperture) delay	Input CLK+ rise to acquisition of data				1.3		ns
t_AJ	Aperture jitter					0.2		ps (rms)
t_OD	Input clock-to data output delay (in addition to t_LAT)	50% of input clock transition to 50% of data transition				3.2		ns
t_LAT	Latency in 1:2 demux non-DES mode⁽⁴⁾	DI, DQ outputs		[4, 5, 6]			34	Input Clock Cycles
	Latency in 1:2 demux non-DES mode⁽⁴⁾	DId, DQd outputs		[4, 5, 6]			35	Input Clock Cycles
	Latency in 1:4 demux DES mode⁽⁴⁾	DI outputs		[4, 5, 6]			34	Input Clock Cycles
		DQ outputs		[4, 5, 6]			34.5
		DId outputs		[4, 5, 6]			35
		DQd outputs		[4, 5, 6]			35.5
	Latency in non-demux non-DES mode⁽⁴⁾	DI outputs		[4, 5, 6]			34	Input Clock Cycles
	Latency in non-demux non-DES mode⁽⁴⁾	DQ outputs		[4, 5, 6]			34	Input Clock Cycles
	Latency in non-demux DES mode⁽⁴⁾	DI outputs		[4, 5, 6]			34	Input Clock Cycles
	Latency in non-demux DES mode⁽⁴⁾	DQ outputs		[4, 5, 6]			34.5	Input Clock Cycles
t_ORR	Over range recovery time	Differential V_IN step from ±1.2 V to 0 V to get accurate conversion				1		Input Clock Cycle
t_WU	PD low-to-rated accuracy conversion (wake-up time)	Non-DES mode				500		ns
t_WU	PD low-to-rated accuracy conversion (wake-up time)	DES mode				1		µs

(1) The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device.

(2) The maximum clock frequency for non-demux mode is 1 GHz.

(3) Typical figures are at T_A = 25°C, and represent most likely parametric norms. Test limits are ensured to Texas Instrument's average outgoing quality level (AOQL).

(4) This parameter is specified by design and/or characterization and is not tested in production.