AutoSync is a new feature which continuously synchronizes the outputs of multiple ADC12D1620 devices in a system. It may be used to synchronize the DCLK and data outputs of one or more secondary ADC12D1620 devices to one primary ADC12D1620. Several advantages of this feature include: no special synchronization pulse required, any upset in synchronization is recovered upon the next DCLK cycle, and the primary/secondary ADC12D1620 devices may be arranged as a binary tree so that any upset quickly propagates out of the system.

An example system is shown in Figure 8-5, which consists of one primary ADC and two secondary ADCs. For simplicity, only one DCLK is shown; in reality, there is DCLKI and DCLKQ, but they are always in phase with one another.

In order to synchronize the DCLK (and data) outputs of multiple ADCs, the DCLKs must transition at the same time, as well as be in phase with one another. The DCLK at each ADC is generated from the CLK after some latency, plus t_OD minus t_AD. Therefore, in order for the DCLKs to transition at the same time, the CLK signal must reach each ADC at the same time. To tune out any differences in the CLK path to each ADC, the t_AD adjust feature may be used. However, using the t_AD adjust feature also affects when the DCLK is produced at the output. If the device is in demux mode, there are four possible phases that each DCLK may be generated on because the typical CLK = 1GHz and DCLK = 250 MHz for this case. The RCLK signal controls the phase of the DCLK, so that each secondary DCLK is on the same phase as the primary DCLK.

The AutoSync feature may only be used through the Control Registers. For more information, see AN-2132 Synchronizing Multiple GSPS ADCs in a System: The AutoSync Feature.