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SNAS518J July 2011 – July 2015 ADC12D1800RF

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4 Specifications

4.1 Absolute Maximum Ratings⁽¹⁾⁽²⁾

	MIN	MAX	UNIT
Supply Voltage (V_A, V_TC, V_DR, V_E)		2.2	V
Supply Difference max(V_A/TC/DR/E)- min(V_A/TC/DR/E)	0	100	mV
Voltage on Any Input Pin (except V_IN±)	−0.15	(V_A + 0.15)	V
V_IN± Voltage Range	–0.5	2.5	V
Ground Difference max(GND_TC/DR/E) -min(GND_TC/DR/E)	0	100	mV
Input Current at Any Pin⁽³⁾	–50	50	mA
ADC12D1800RF Package Power Dissipation at T_A ≤ 65°C⁽³⁾		4.95	W
Storage temperature, T_stg	–65	150	°C

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. There is no specification of operation at the Absolute Maximum Ratings. Recommended Operating Conditions indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.

(2) All voltages are measured with respect to GND = GND_TC = GND_DR = GND_E = 0V, unless otherwise specified.

(3) When the input voltage at any pin exceeds the power supply limits, i.e. less than GND or greater than V_A, the current at that pin should be limited to 50 mA. In addition, over-voltage at a pin must adhere to the maximum voltage limits. Simultaneous over-voltage at multiple pins requires adherence to the maximum package power dissipation limits. These dissipation limits are calculated using JEDEC JESD51-7 thermal model. Higher dissipation may be possible based on specific customer thermal situation and specified package thermal resistances from junction to case.

4.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	±2500	V
		Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	±1000
		Machine model (MM)	±250

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

4.3 Recommended Operating Conditions⁽¹⁾⁽²⁾

		MIN	MAX	UNIT
T_A	Ambient Temperature Range: ADC12D1800RF (Standard JEDEC thermal model)	–40	50	°C
T_A	Ambient Temperature Range: ADC12D1800RF (Enhanced thermal model / heatsink)	–40	50	°C
T_J	Junction Temperature Range - applies only to maximum operating speed	120		°C
Supply Voltage (V_A, V_TC, V_E)		1.8	2	V
Driver Supply Voltage (V_DR)		1.8	V_A	V
V_IN± Voltage Range⁽³⁾		–0.4	2.4 (d.c.-coupled)	V
V_IN± Differential Voltage Range⁽⁴⁾		1.0 (d.c.-coupled at 100% duty cycle) 2.0 (d.c.-coupled a t20% duty cycle) 2.8 (d.c.-coupled at 10% duty cycle)		V
V_IN± Current Range⁽³⁾		–50	50 peak (a.c.-coupled)	mA
V_IN± Power		15.3 (maintaining common mode voltage, a.c.-coupled) 17.1 (not maintaining common mode voltage, a.c.-coupled)		dBm
Ground Difference max(GND_TC/DR/E) -min(GND_TC/DR/E)			0	V
CLK± Voltage Range		0	V_A	V
Differential CLK Amplitude V_P-P		0.4	2	V
Common Mode Input Voltage V_CMI		V_CMO - 150	V_CMO + 150	mV

(2) All voltages are measured with respect to GND = GND_TC = GND_DR = GND_E = 0V, unless otherwise specified.

(3) Proper common mode voltage must be maintained to ensure proper output codes, especially during input overdrive.

(4) This rating is intended for d.c.-coupled applications; the voltages listed may be safely applied to V_IN± for the life-time duty-cycle of the part.

4.4 Thermal Information

THERMAL METRIC⁽¹⁾		ADC12D1800RF	UNIT
		NXA
		292 PINS
R_θJA	Junction-to-ambient thermal resistance	16	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	2.9	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	2.5	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and C Package Thermal Metrics application report, SPRA953.

4.5 Converter Electrical Characteristics: Static Converter Characteristics

Unless otherwise specified, the following apply after calibration for V_A = V_DR = V_TC = V_E = +1.9 V; I- and Q-channels, AC-coupled, unused channel terminated to AC ground, FSR Pin = High; C_L = 10 pF; Differential, AC coupled Sine Wave Sampling Clock, f_CLK = 1.8 GHz at 0.5 V_P-P with 50% duty cycle (as specified); V_BG = Floating; Extended Control Mode with Register 6h written to 1C0Eh; Rext = Rtrim = 3300Ω ± 0.1%; Analog Signal Source Impedance = 100Ω Differential; 1:2 Demultiplex Non-DES Mode; Duty Cycle Stabilizer on. Limits are T_A = 25°C, unless otherwise noted.⁽¹⁾⁽²⁾⁽³⁾

PARAMETER		TEST CONDITIONS	ADC12D1800RF		UNIT
PARAMETER		TEST CONDITIONS	TYP	LIM	UNIT
	Resolution with No Missing Codes	T_A = T_MIN to T_MAX, T_J < 105°C		12	bits
INL	Integral Non-Linearity (Best fit)	1 MHz DC-coupled over-ranged sine wave	±2.5		LSB
DNL	Differential Non-Linearity	1 MHz DC-coupled over-ranged sine wave	±0.4		LSB
V_OFF	Offset Error		5		LSB
V_OFF_ADJ	Input Offset Adjustment Range	Extended Control Mode	±45		mV
PFSE	Positive Full-Scale Error	See ⁽⁴⁾, T_A = T_MIN to T_MAX, T_J < 105°C		±25	mV
NFSE	Negative Full-Scale Error	See ⁽⁴⁾, T_A = T_MIN to T_MAX, T_J < 105°C		±25	mV
	Out-of-Range Output Code⁽⁵⁾	(V_IN+) − (V_IN−) > + Full Scale, T_A = T_MIN to T_MAX, T_J < 105°C		4095
	Out-of-Range Output Code⁽⁵⁾	(V_IN+) − (V_IN−) < − Full Scale, T_A = T_MIN to T_MAX, T_J < 105°C		0

(1) The analog inputs, labeled "I/O", are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device.
ADC12D1800RF 30164304.gif

(2) To ensure accuracy, it is required that V_A, V_TC, V_E and V_DR be well-bypassed. Each supply pin must be decoupled with separate bypass capacitors.

(3) Typical figures are at T_A = 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average Outgoing Quality Level).

(4) Calculation of Full-Scale Error for this device assumes that the actual reference voltage is exactly its nominal value. Full-Scale Error for this device, therefore, is a combination of Full-Scale Error and Reference Voltage Error. See Figure 4-1. For relationship between Gain Error and Full-Scale Error, see Specification Definitions for Gain Error.

(5) This parameter is specified by design and is not tested in production.

4.6 Converter Electrical Characteristics: Dynamic Converter Characteristics⁽¹⁾

Limits apply T_A = T_MIN to T_MAX, T_J < 105°C

PARAMETER		TEST CONDITIONS	ADC12D1800RF			UNIT
PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
	Bandwidth	Non-DES Mode, DESCLKIQ Mode
		-3 dB⁽²⁾		2.7		GHz
		-6 dB		3.1		GHz
		-9 dB		3.5		GHz
		-12 dB		4.0		GHz
		DESI Mode, DESQ Mode
		-3 dB⁽²⁾		1.2		GHz
		-6 dB		2.3		GHz
		-9 dB		2.7		GHz
		-12 dB		3.0		GHz
		DESIQ Mode
		-3 dB⁽²⁾		1.75		GHz
		-6 dB		2.7		GHz
	Gain Flatness	Non-DES Mode
		D.C. to Fs/2		±0.4		dB
		D.C. to Fs		±1.1		dB
		D.C. to 3Fs/2		±1.7		dB
		D.C. to 2Fs		±5.7		dB
		DESI, DESQ Mode
		D.C. to Fs/2		±2.7		dB
		D.C. to Fs		±9.2		dB
		DESIQ Mode
		D.C. to Fs/2		±1.6		dB
		DESCLKIQ Mode
		D.C. to Fs/2		±1.2		dB
CER	Code Error Rate			10^-18		Error/ Sample
IMD₃	3rd order Intermodulation Distortion	DES Mode
		F_IN = 2670 MHz ± 2.5MHz at -13 dBFS		-75		dBFS
		F_IN = 2670 MHz ± 2.5MHz at -13 dBFS		-62		dBc
		F_IN = 2070 MHz ± 2.5MHz at -13 dBFS		-85		dBFS
		F_IN = 2070 MHz ± 2.5MHz at -13 dBFS		-72		dBc
		F_IN = 2670 MHz ± 2.5MHz at -16 dBFS		-80		dBFS
		F_IN = 2670 MHz ± 2.5MHz at -16 dBFS		-64		dBc
		F_IN = 2070 MHz ± 2.5MHz at -16 dBFS		-83		dBFS
		F_IN = 2070 MHz ± 2.5MHz at -16 dBFS		-67		dBc
	Noise Floor Density	50Ω single-ended termination, DES Mode		-155.0		dBm/Hz
	Noise Floor Density	50Ω single-ended termination, DES Mode		-154.0		dBFS/Hz
NON-DES MODE⁽³⁾⁽⁴⁾⁽⁵⁾
ENOB	Effective Number of Bits	A_IN = 125 MHz at -0.5 dBFS		9.3		bits
		A_IN = 248 MHz at -0.5 dBFS		9.3		bits
		A_IN = 498 MHz at -0.5 dBFS	8.4	9.3		bits
		A_IN = 1147 MHz at -0.5 dBFS		8.7		bits
		A_IN = 1448 MHz at -0.5 dBFS		8.7		bits
SINAD	Signal-to-Noise Plus Distortion Ratio	A_IN = 125 MHz at -0.5 dBFS		57.7		dB
		A_IN = 248 MHz at -0.5 dBFS		57.7		dB
		A_IN = 498 MHz at -0.5 dBFS	52.1	57.7		dB
		A_IN = 1147 MHz at -0.5 dBFS		54.1		dB
		A_IN = 1448 MHz at -0.5 dBFS		54		dB
SNR	Signal-to-Noise Ratio	A_IN = 125 MHz at -0.5 dBFS		58.6		dB
		A_IN = 248 MHz at -0.5 dBFS		58.2		dB
		A_IN = 498 MHz at -0.5 dBFS	52.9	58.1		dB
		A_IN = 1147 MHz at -0.5 dBFS		54.9		dB
		A_IN = 1448 MHz at -0.5 dBFS		54.3		dB
THD	Total Harmonic Distortion	A_IN = 125 MHz at -0.5 dBFS		-64.9		dB
		A_IN = 248 MHz at -0.5 dBFS		-65.7		dB
		A_IN = 498 MHz at -0.5 dBFS		-67	–60	dB
		A_IN = 1147 MHz at -0.5 dBFS		-61.5		dB
		A_IN = 1448 MHz at -0.5 dBFS		-64.9		dB
2nd Harm	Second Harmonic Distortion	A_IN = 125 MHz at -0.5 dBFS		-68.8		dBc
		A_IN = 248 MHz at -0.5 dBFS		-85.6		dBc
		A_IN = 498 MHz at -0.5 dBFS		-72.5		dBc
		A_IN = 1147 MHz at -0.5 dBFS		-81.2		dBc
		A_IN = 1448 MHz at -0.5 dBFS		-70.4		dBc
3rd Harm	Third Harmonic Distortion	A_IN = 125 MHz at -0.5 dBFS		-70.4		dBc
		A_IN = 248 MHz at -0.5 dBFS		-67.5		dBc
		A_IN = 498 MHz at -0.5 dBFS		-69.8		dBc
		A_IN = 1147 MHz at -0.5 dBFS		-70.4		dBc
		A_IN = 1448 MHz at -0.5 dBFS		-73		dBc
SFDR	Spurious-Free Dynamic Range	A_IN = 125 MHz at -0.5 dBFS		68.1		dBc
		A_IN = 248 MHz at -0.5 dBFS		67		dBc
		A_IN = 498 MHz at -0.5 dBFS	54	71.7		dBc
		A_IN = 1147 MHz at -0.5 dBFS		60		dBc
		A_IN = 1448 MHz at -0.5 dBFS		61		dBc
DES MODE⁽³⁾⁽⁶⁾⁽⁴⁾⁽⁵⁾
ENOB	Effective Number of Bits	A_IN = 125 MHz at -0.5 dBFS		9		bits
		A_IN = 248 MHz at -0.5 dBFS		9		bits
		A_IN = 498 MHz at -0.5 dBFS		9.1		bits
		A_IN = 1147 MHz at -0.5 dBFS		8.6		bits
		A_IN = 1448 MHz at -0.5 dBFS		8.6		bits
SINAD	Signal-to-Noise Plus Distortion Ratio	A_IN = 125 MHz at -0.5 dBFS		56		dB
		A_IN = 248 MHz at -0.5 dBFS		56		dB
		A_IN = 498 MHz at -0.5 dBFS		56.5		dB
		A_IN = 1147 MHz at -0.5 dBFS		53.6		dB
		A_IN = 1448 MHz at -0.5 dBFS		53.6		dB
SNR	Signal-to-Noise Ratio	A_IN = 125 MHz at -0.5 dBFS		57.2		dB
		A_IN = 248 MHz at -0.5 dBFS		57.3		dB
		A_IN = 498 MHz at -0.5 dBFS		57.3		dB
		A_IN = 1147 MHz at -0.5 dBFS		54.7		dB
		A_IN = 1448 MHz at -0.5 dBFS		54		dB
THD	Total Harmonic Distortion	A_IN = 125 MHz at -0.5 dBFS		-62.1		dB
		A_IN = 248 MHz at -0.5 dBFS		-61.6		dB
		A_IN = 498 MHz at -0.5 dBFS		-64		dB
		A_IN = 1147 MHz at -0.5 dBFS		-59.7		dB
		A_IN = 1448 MHz at -0.5 dBFS		-62.8		dB
2nd Harm	Second Harmonic Distortion	A_IN = 125 MHz at -0.5 dBFS		-82		dBc
		A_IN = 248 MHz at -0.5 dBFS		-78.5		dBc
		A_IN = 498 MHz at -0.5 dBFS		-71.1		dBc
		A_IN = 1147 MHz at -0.5 dBFS		-76.9		dBc
		A_IN = 1448 MHz at -0.5 dBFS		-75.3		dBc
3rd Harm	Third Harmonic Distortion	A_IN = 125 MHz at -0.5 dBFS		-64.7		dBc
		A_IN = 248 MHz at -0.5 dBFS		-62.5		dBc
		A_IN = 498 MHz at -0.5 dBFS		-71.4		dBc
		A_IN = 1147 MHz at -0.5 dBFS		-60.4		dBc
		A_IN = 1448 MHz at -0.5 dBFS		-65.8		dBc
SFDR	Spurious-Free Dynamic Range	A_IN = 125 MHz at -0.5 dBFS		64.2		dBc
		A_IN = 248 MHz at -0.5 dBFS		62.4		dBc
		A_IN = 498 MHz at -0.5 dBFS		68.1		dBc
		A_IN = 1147 MHz at -0.5 dBFS		60.3		dBc
		A_IN = 1448 MHz at -0.5 dBFS		63.6		dBc

(1) This parameter is specified by design and/or characterization and is not tested in production.

(2) The -3 dB point is the traditional Full-Power Bandwidth (FPBW) specification. Although the insertion loss is approximately half the power at this frequency, the dynamic performance of the ADC does not necessarily begin to degrade to a level below which it may be effectively used in an application. The ADC may be used at input frequencies above the -3 dB FPBW point, for example, into the 3rd Nyquist zone. Depending on system requirements, it is only necessary to compensate for the insertion loss.

(3) The Dynamic Specifications are ensured for room to hot ambient temperature only (25°C to 85°C). Refer to the plots of the dynamic performance vs. temperature in Typical Performance Plots to see typical performance from cold to room temperature (-40°C to 25°C).

(4) The Fs/2 spur was removed from all the dynamic performance specifications.

(5) Typical dynamic performance is only tested at Fin = 498 MHz; other input frequencies are specified by design and / or characterization and are not tested in production.

(6) These measurements were taken in Extended Control Mode (ECM) with the DES Timing Adjust feature enabled (Addr: 7h). This feature is used to reduce the interleaving timing spur amplitude, which occurs at fs/2-fin, and thereby increase the SFDR, SINAD and ENOB.

4.7 Converter Electrical Characteristics: Analog Input / Output and Reference Characteristics

MIN and MAX limits apply T_A = T_MIN to T_MAX, T_J < 105°C

PARAMETER		TEST CONDITIONS	ADC12D1800RF			UNIT
PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
ANALOG INPUTS
V_{IN_FSR}	Analog Differential Input Full Scale Range	Non-Extended Control Mode
		FSR Pin High	740	800	860	mV_P-P
		Extended Control Mode
		FM(14:0) = 4000h (default)		800		mV_P-P
		FM(14:0) = 7FFFh		1000		mV_P-P
C_IN	Analog Input Capacitance, Non-DES Mode⁽²⁾⁽¹⁾	Differential		0.02		pF
	Analog Input Capacitance, Non-DES Mode⁽²⁾⁽¹⁾	Each input pin to ground		1.6		pF
	Analog Input Capacitance, DES Mode⁽²⁾⁽¹⁾	Differential		0.08		pF
	Analog Input Capacitance, DES Mode⁽²⁾⁽¹⁾	Each input pin to ground		2.2		pF
R_IN	Differential Input Resistance		91	100	109	Ω
COMMON MODE OUTPUT
V_CMO	Common Mode Output Voltage	I_CMO = ±100 µA	1.15	1.25	1.35	V
TC_V_CMO	Common Mode Output Voltage Temperature Coefficient	I_CMO = ±100 µA⁽³⁾		38		ppm/°C
V_{CMO_LVL}	V_CMO input threshold to set DC-coupling Mode	See ⁽³⁾		0.63		V
C_L_V_CMO	Maximum V_CMO Load Capacitance	See ⁽²⁾			80	pF
BANDGAP REFERENCE
V_BG	Bandgap Reference Output Voltage	I_BG = ±100 µA	1.15	1.25	1.35	V
TC_V_BG	Bandgap Reference Voltage Temperature Coefficient	I_BG = ±100 µA⁽³⁾		32		ppm/°C
C_L_V_BG	Maximum Bandgap Reference load Capacitance	See ⁽²⁾			80	pF

(1) The differential and pin-to-ground input capacitances are lumped capacitance values from design; they are defined as shown below.

ADC12D1800RF 30164395.gif

(2) This parameter is specified by design and is not tested in production.

(3) This parameter is specified by design and/or characterization and is not tested in production.

4.8 Converter Electrical Characteristics: I-Channel to Q-Channel Characteristics

PARAMETER		TEST CONDITIONS	ADC12D1800RF		UNIT
PARAMETER		TEST CONDITIONS	TYP	LIM	UNIT
	Offset Match	See ⁽¹⁾	2		LSB
	Positive Full-Scale Match	Zero offset selected in Control Register	2		LSB
	Negative Full-Scale Match	Zero offset selected in Control Register	2		LSB
	Phase Matching (I, Q)	f_IN = 1.0 GHz⁽¹⁾	< 1		Degree
X-TALK	Crosstalk from I-channel (Aggressor) to Q-channel (Victim)	Aggressor = 867 MHz F.S. Victim = 100 MHz F.S.	−70		dB
X-TALK	Crosstalk from Q-channel (Aggressor) to I-channel (Victim)	Aggressor = 867 MHz F.S. Victim = 100 MHz F.S.	−70		dB

(1) This parameter is specified by design and/or characterization and is not tested in production.

4.9 Converter Electrical Characteristics: Sampling Clock Characteristics

Limits apply T_A = T_MIN to T_MAX, T_J < 105°C

PARAMETER		TEST CONDITIONS	ADC12D1800RF			UNIT
PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_{IN_CLK}	Differential Sampling Clock Input Level⁽¹⁾	Sine Wave Clock Differential Peak-to-Peak	0.4	0.6	2.0	V_P-P
V_{IN_CLK}	Differential Sampling Clock Input Level⁽¹⁾	Square Wave Clock Differential Peak-to-Peak	0.4	0.6	2.0	V_P-P
C_{IN_CLK}	Sampling Clock Input Capacitance⁽²⁾	Differential		0.1		pF
C_{IN_CLK}	Sampling Clock Input Capacitance⁽²⁾	Each input to ground		1		pF
R_{IN_CLK}	Sampling Clock Differential Input Resistance	See ⁽¹⁾		100		Ω

(1) This parameter is specified by design and/or characterization and is not tested in production.

(2) This parameter is specified by design and is not tested in production.

4.10 Converter Electrical Characteristics: AutoSync Feature Characteristics

PARAMETER		TEST CONDITIONS	ADC12D1800RF		UNIT
PARAMETER		TEST CONDITIONS	TYP	LIM	UNIT
V_{IN_RCLK}	Differential RCLK Input Level⁽¹⁾	Differential Peak-to-Peak	360		mV_P-P
C_{IN_RCLK}	RCLK Input Capacitance⁽¹⁾	Differential	0.1		pF
C_{IN_RCLK}	RCLK Input Capacitance⁽¹⁾	Each input to ground	1		pF
R_{IN_RCLK}	RCLK Differential Input Resistance	See ⁽¹⁾	100		Ω
I_{IH_RCLK}	Input Leakage Current; V_IN = V_A		22		µA
I_{IL_RCLK}	Input Leakage Current; V_IN = GND		-33		µA
V_{O_RCOUT}	Differential RCOut Output Voltage		360		mV

(1) This parameter is specified by design and/or characterization and is not tested in production.

4.11 Converter Electrical Characteristics: Digital Control and Output Pin Characteristics

Limits apply T_A = T_MIN to T_MAX, T_J < 105°C

PARAMETER		TEST CONDITIONS	ADC12D1800RF			UNIT
PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
DIGITAL CONTROL PINS (DES, CalDly, CAL, PDI, PDQ, TPM, NDM, FSR, DDRPh, ECE, SCLK, SDI, SCS)
V_IH	Logic High Input Voltage		0.7×V_A		0.3×V_A	V
V_IL	Logic Low Input Voltage		0.7×V_A		0.3×V_A	V
I_IH	Input Leakage Current; V_IN = V_A			0.02		μA
I_IL	Input Leakage Current; V_IN = GND	FSR, CalDly, CAL, NDM, TPM, DDRPh, DES		-0.02		μA
		SCS, SCLK, SDI		-17		μA
		PDI, PDQ, ECE		-38		μA
C_{IN_DIG}	Digital Control Pin Input Capacitance⁽²⁾	Measured from each control pin to GND		1.5		pF
DIGITAL OUTPUT PINS (Data, DCLKI, DCLKQ, ORI, ORQ)
V_OD	LVDS Differential Output Voltage	V_BG = Floating, OVS = High	400	630	800	mV_P-P
		V_BG = Floating, OVS = Low	230	460	630	mV_P-P
		V_BG = V_A, OVS = High		670		mV_P-P
		V_BG = V_A, OVS = Low		500		mV_P-P
ΔV_{O DIFF}	Change in LVDS Output Swing Between Logic Levels			±1		mV
V_OS	Output Offset Voltage⁽¹⁾	V_BG = Floating		0.8		V
V_OS	Output Offset Voltage⁽¹⁾	V_BG = V_A		1.2		V
ΔV_OS	Output Offset Voltage Change Between Logic Levels	See ⁽²⁾		±1		mV
I_OS	Output Short Circuit Current⁽¹⁾	V_BG = Floating; D+ and D− connected to 0.8V		±4		mA
Z_O	Differential Output Impedance	See ⁽¹⁾		100		Ω
V_OH	Logic High Output Level	CalRun, I_OH = −100 µA,⁽¹⁾ SDO, I_OH = −400 µA⁽¹⁾		1.65		V
V_OL	Logic Low Output Level	CalRun, I_OL = 100 µA,⁽¹⁾ SDO, I_OL = 400 µA⁽¹⁾		0.15		V
DIFFERENTIAL DCLK RESET PINs (DCLK_RST)
V_{CMI_DRST}	DCLK_RST Common Mode Input Voltage	See ⁽¹⁾		1.25		V
V_{ID_DRST}	Differential DCLK_RST Input Voltage	See ⁽¹⁾		V_{IN_CLK}		V_P-P
R_{IN_DRST}	Differential DCLK_RST Input Resistance	See ⁽¹⁾		100		Ω

(1) This parameter is specified by design and/or characterization and is not tested in production.

(2) This parameter is specified by design and is not tested in production.

4.12 Converter Electrical Characteristics: Power Supply Characteristics

Limits apply T_A = T_MIN to T_MAX, T_J < 105°C

PARAMETER		TEST CONDITIONS	ADC12D1800RF		UNIT
PARAMETER		TEST CONDITIONS	TYP	MAX	UNIT
I_A	Analog Supply Current	PDI = PDQ = Low	1360		mA
		PDI = Low; PDQ = High	745		mA
		PDI = High; PDQ = Low	745		mA
		PDI = PDQ = High	2.7		mA
I_TC	Track-and-Hold and Clock Supply Current	PDI = PDQ = Low	515		mA
		PDI = Low; PDQ = High	305		mA
		PDI = High; PDQ = Low	305		mA
		PDI = PDQ = High	650		µA
I_DR	Output Driver Supply Current	PDI = PDQ = Low	275		mA
		PDI = Low; PDQ = High	145		mA
		PDI = High; PDQ = Low	145		mA
		PDI = PDQ = High	6		µA
I_E	Digital Encoder Supply Current	PDI = PDQ = Low	110		mA
		PDI = Low; PDQ = High	65		mA
		PDI = High; PDQ = Low	65		mA
		PDI = PDQ = High	34		µA
I_TOTAL	Total Supply Current	1:2 Demux Mode PDI = PDQ = Low	2260	2481	mA
I_TOTAL	Total Supply Current	Non-Demux Mode PDI = PDQ = Low	2220		mA
P_C	Power Consumption	1:2 Demux Mode
		PDI = PDQ = Low	4.29	4.7	W
		PDI = Low; PDQ = High	2.39		W
		PDI = High; PDQ = Low	2.39		W
		PDI = PDQ = High	6.5		mW
		Non-Demux Mode
		PDI = PDQ = Low	4.22		W

4.13 Converter Electrical Characteristics: AC Electrical Characteristics

Limits apply for T_A = T_MIN to T_MAX, T_J < 105°C

PARAMETER		TEST CONDITIONS	ADC12D1800RF			UNIT
PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SAMPLING CLOCK (CLK)
f_{CLK (max)}	Maximum Sampling Clock Frequency				1.8	GHz
f_{CLK (min)}	Minimum Sampling Clock Frequency	Non-DES Mode; LFS = 0b			300	MHz
		Non-DES Mode; LFS = 1b			150	MHz
		DES Mode			500	MHz
	Sampling Clock Duty Cycle	f_CLK(min) ≤ f_CLK ≤ f_CLK(max)⁽¹⁾	20%	50%	80%
t_CL	Sampling Clock Low Time	See ⁽²⁾	111	278		ps
t_CH	Sampling Clock High Time	See ⁽²⁾	111	278		ps
DATA CLOCK (DCLKI, DCLKQ)
	DCLK Duty Cycle	See ⁽²⁾	45%	50%	55%
t_SR	Setup Time DCLK_RST±	See ⁽¹⁾		45		ps
t_HR	Hold Time DCLK_RST±	See ⁽¹⁾		45		ps
t_PWR	Pulse Width DCLK_RST±	See ⁽²⁾	5			Sampling Clock Cycles
t_{SYNC_DLY}	DCLK Synchronization Delay	90° Mode⁽²⁾			4	Sampling Clock Cycles
t_{SYNC_DLY}	DCLK Synchronization Delay	0° Mode⁽²⁾			5	Sampling Clock Cycles
t_LHT	Differential Low-to-High Transition Time	10%-to-90%, C_L = 2.5 pF⁽¹⁾		200		ps
t_HLT	Differential High-to-Low Transition Time	10%-to-90%, C_L = 2.5 pF⁽¹⁾		200		ps
t_SU	Data-to-DCLK Setup Time	90° Mode⁽²⁾		430		ps
t_H	DCLK-to-Data Hold Time	90° Mode⁽²⁾		430		ps
t_OSK	DCLK-to-Data Output Skew	50% of DCLK transition to 50% of Data transition⁽²⁾		±50		ps
DATA INPUT-TO-OUTPUT
t_AD	Aperture Delay⁽¹⁾	Sampling CLK+ Rise to Acquisition of Data		1.29		ns
t_AJ	Aperture Jitter	See ⁽¹⁾		0.2		ps (rms)
t_OD	Sampling Clock-to Data Output Delay (in addition to Latency)	50% of Sampling Clock transition to 50% of Data transition⁽¹⁾		3.2		ns
t_LAT	Latency in 1:2 Demux Non-DES Mode⁽²⁾	DI, DQ Outputs			34	Sampling Clock Cycles
	Latency in 1:2 Demux Non-DES Mode⁽²⁾	DId, DQd Outputs			35
	Latency in 1:4 Demux DES Mode⁽²⁾	DI Outputs			34
		DQ Outputs			34.5
		DId Outputs			35
		DQd Outputs			35.5
	Latency in Non-Demux Non-DES Mode⁽²⁾	DI Outputs			34
	Latency in Non-Demux Non-DES Mode⁽²⁾	DQ Outputs			34
	Latency in Non-Demux DES Mode⁽²⁾	DI Outputs			34
	Latency in Non-Demux DES Mode⁽²⁾	DQ Outputs			34.5
t_ORR	Over Range Recovery Time	Differential V_IN step from ±1.2V to 0V to accurate conversion⁽¹⁾		1		Sampling Clock Cycle
t_WU	Wake-Up Time (PDI/PDQ low to Rated Accuracy Conversion)	Non-DES Mode⁽²⁾		500		ns
t_WU	Wake-Up Time (PDI/PDQ low to Rated Accuracy Conversion)	DES Mode⁽²⁾		1		µs

(1) This parameter is specified by design and/or characterization and is not tested in production.

(2) This parameter is specified by design and is not tested in production.

4.14 Converter Electrical Characteristics: Serial Port Interface

Limits apply for T_A = T_MIN to T_MAX, T_J < 105°C

PARAMETER		TEST CONDITIONS	ADC12D1800RF		UNIT
PARAMETER		TEST CONDITIONS	TYP	MIN	UNIT
f_SCLK	Serial Clock Frequency	See ⁽²⁾	15		MHz
	Serial Clock Low Time			30	ns
	Serial Clock High Time			30	ns
t_SSU	Serial Data-to-Serial Clock Rising Setup Time	See ⁽¹⁾	2.5		ns
t_SH	Serial Data-to-Serial Clock Rising Hold Time	See ⁽²⁾	1		ns
t_SCS	SCS-to-Serial Clock Rising Setup Time	See ⁽¹⁾	2.5		ns
t_HCS	SCS-to-Serial Clock Falling Hold Time	See ⁽¹⁾	1.5		ns
t_BSU	Bus turn-around time	See ⁽¹⁾	10		ns

(1) This parameter is specified by design and/or characterization and is not tested in production.

(2) This parameter is specified by design and is not tested in production.

4.15 Converter Electrical Characteristics Calibration

Limits apply for T_A = T_MIN to T_MAX, T_J < 105°C

PARAMETER		TEST CONDITIONS	ADC12D1800RF			UNIT
PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_CAL	Calibration Cycle Time	Non-ECM		4.1·10⁷		Sampling Clock Cycles
		ECM CSS = 0b
		ECM CSS = 1b
t_{CAL_L}	CAL Pin Low Time	See ⁽¹⁾	1280			Sampling Clock Cycles
t_{CAL_H}	CAL Pin High Time	See ⁽¹⁾	1280			Sampling Clock Cycles
t_CalDly	Calibration delay determined by CalDly Pin⁽¹⁾	CalDly = Low			2²⁴	Sampling Clock Cycles
t_CalDly	Calibration delay determined by CalDly Pin⁽¹⁾	CalDly = High			2³⁰	Sampling Clock Cycles

(1) This parameter is specified by design and is not tested in production.

Figure 4-1 Input / Output Transfer Characteristic

*The timing for these figures is shown for the one input only (I or Q). However, both I- and Q-inputs may be used. For this case, the I-channel functions precisely the same as the Q-channel, with VinI, DCLKI, DId and DI instead of VinQ, DCLKQ, DQd and DQ. Both I- and Q-channel use the same CLK.

Figure 4-2 Clocking in 1:2 Demux Non-DES Mode*

Figure 4-3 Clocking in Non-Demux Non-DES Mode*

Figure 4-4 Clocking in 1:4 Demux DES Mode*

Figure 4-5 Clocking in Non-Demux Mode DES Mode*

Figure 4-6 Data Clock Reset Timing (Demux Mode)

Figure 4-7 Power-on and On-Command Calibration Timing

Figure 4-8 Serial Interface Timing

4.16 Typical Characteristics

V_A= V_DR = V_TC = V_E = 1.9V, f_CLK = 1.8 GHz, f_IN = 498 MHz, T_A= 25°C, I-channel, 1:2 Demux Non-DES Mode (1:1 Demux Non-DES Mode has similar performance), unless otherwise stated.