The clocking subsystem is largely responsible for achieving multi-device synchronization and deterministic latency. The device uses the JESD204C subclass-1 method to achieve deterministic latency and synchronization. Subclass 1 requires that the SYSREF signal be captured by a deterministic clock (CLK± or SE_CLK) edge at each system power-on and at each device in the system. This requirement imposes setup and hold constraints on SYSREF relative to CLK±, which can be difficult to meet at giga-sample clock rates over all system operating conditions. The device includes a number of features to simplify this synchronization process and to relax system timing constraints:

• The ADC12QJ1600-Q1 includes an integrated PLL and VCO to generate the high frequency sampling clock, relaxing the timing requirement by requiring timing to only be met relative to a low frequency reference clock.
• A SYSREF position detector (relative to CLK± or SE_CLK) and selectable SYSREF sampling position aid the user in meeting setup and hold times over all conditions; see the SYSREF Windowing section