ZHCSOI5A October   2021  – November 2024 ADC12DJ1600 , ADC12QJ1600 , ADC12SJ1600

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: DC Specifications
    6. 6.6  Electrical Characteristics: Power Consumption
    7. 6.7  Electrical Characteristics: AC Specifications
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
        1. 7.3.1.1 Analog Input Protection
        2. 7.3.1.2 Full-Scale Voltage (VFS) Adjustment
        3. 7.3.1.3 Analog Input Offset Adjust
        4. 7.3.1.4 ADC Core
          1. 7.3.1.4.1 ADC Theory of Operation
          2. 7.3.1.4.2 ADC Core Calibration
          3. 7.3.1.4.3 Analog Reference Voltage
          4. 7.3.1.4.4 ADC Over-range Detection
          5. 7.3.1.4.5 Code Error Rate (CER)
      2. 7.3.2 Temperature Monitoring Diode
      3. 7.3.3 Timestamp
      4. 7.3.4 Clocking
        1. 7.3.4.1 Converter PLL (C-PLL) for Sampling Clock Generation
        2. 7.3.4.2 LVDS Clock Outputs (PLLREFO±, TRIGOUT±)
        3. 7.3.4.3 Optional CMOS Clock Outputs (ORC, ORD)
        4. 7.3.4.4 SYSREF for JESD204C Subclass-1 Deterministic Latency
          1. 7.3.4.4.1 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          2. 7.3.4.4.2 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
      5. 7.3.5 JESD204C Interface
        1. 7.3.5.1  Transport Layer
        2. 7.3.5.2  Scrambler
        3. 7.3.5.3  Link Layer
        4. 7.3.5.4  8B or 10B Link Layer
          1. 7.3.5.4.1 Data Encoding (8B or 10B)
          2. 7.3.5.4.2 Multiiframes and the Local Multiframe Clock (LMFC)
          3. 7.3.5.4.3 Code Group Synchronization (CGS)
          4. 7.3.5.4.4 Initial Lane Alignment Sequence (ILAS)
          5. 7.3.5.4.5 Frame and Multiframe Monitoring
        5. 7.3.5.5  64B or 66B Link Layer
          1. 7.3.5.5.1 64B or 66B Encoding
          2. 7.3.5.5.2 Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)
            1. 7.3.5.5.2.1 Block, Multiblock and Extended Multiblock Alignment using Sync Header
              1. 7.3.5.5.2.1.1 Cyclic Redundancy Check (CRC) Mode
              2. 7.3.5.5.2.1.2 Forward Error Correction (FEC) Mode
          3. 7.3.5.5.3 Initial Lane Alignment
          4. 7.3.5.5.4 Block, Multiblock and Extended Multiblock Alignment Monitoring
        6. 7.3.5.6  Physical Layer
          1. 7.3.5.6.1 SerDes Pre-Emphasis
        7. 7.3.5.7  JESD204C Enable
        8. 7.3.5.8  Multi-Device Synchronization and Deterministic Latency
        9. 7.3.5.9  Operation in Subclass 0 Systems
        10. 7.3.5.10 Alarm Monitoring
          1. 7.3.5.10.1 Clock Upset Detection
          2. 7.3.5.10.2 FIFO Upset Detection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Low Power Mode and High Performance Mode
      2. 7.4.2 JESD204C Modes
        1. 7.4.2.1 JESD204C Transport Layer Data Formats
        2. 7.4.2.2 64B or 66B Sync Header Stream Configuration
        3. 7.4.2.3 Redundant Data Mode (Alternate Lanes)
      3. 7.4.3 Power-Down Modes
      4. 7.4.4 Test Modes
        1. 7.4.4.1 Serializer Test-Mode Details
        2. 7.4.4.2 PRBS Test Modes
        3. 7.4.4.3 Clock Pattern Mode
        4. 7.4.4.4 Ramp Test Mode
        5. 7.4.4.5 Short and Long Transport Test Mode
          1. 7.4.4.5.1 Short Transport Test Pattern
        6. 7.4.4.6 D21.5 Test Mode
        7. 7.4.4.7 K28.5 Test Mode
        8. 7.4.4.8 Repeated ILA Test Mode
        9. 7.4.4.9 Modified RPAT Test Mode
      5. 7.4.5 Calibration Modes and Trimming
        1. 7.4.5.1 Foreground Calibration Mode
        2. 7.4.5.2 Background Calibration Mode
        3. 7.4.5.3 Low-Power Background Calibration (LPBG) Mode
      6. 7.4.6 Offset Calibration
      7. 7.4.7 Trimming
    5. 7.5 Programming
      1. 7.5.1 Using the Serial Interface
      2. 7.5.2 SCS
      3. 7.5.3 SCLK
      4. 7.5.4 SDI
      5. 7.5.5 SDO
      6. 7.5.6 Streaming Mode
      7. 7.5.7 SPI_Register_Map Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Light Detection and Ranging (LiDAR) Digitizer
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Analog Front-End Requirements
          2. 8.2.1.2.2 Calculating Clock and SerDes Frequencies
        3. 8.2.1.3 Application Curves
    3. 8.3 Initialization Set Up
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 Power Sequencing
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 静电放电警告
    6. 9.6 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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订购信息

7.4.2.1 JESD204C Transport Layer Data Formats

The ADC core output samples are formatted in a specific fashion for each JMODE setting based on the transport layer settings for that JMODE. The following tables show the specific mapping formats for a single frame for each JMODE. The symbol definitions used in the JMODE tables is provided in Table 7-19. In all mappings the tail bits (T) are 0 (zero). All samples are formatted as MSB first, LSB last.

Table 7-19 JMODE Table Symbol Definitions
NOTATIONDESCRIPTION
AnSample n from channel A
BnSample n from channel B
CnSample n from channel C
DnSample n from channel D
TTail bits, always set to 0
Table 7-20 JMODE 0 (12-bit, 8/4/2 lanes, 8B/10B)
OCTET 0 1 2 3 4 5 6 7
NIBBLE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 A0 A2 A4 A6 A8 T
D1 A1 A3 A5 A7 A9 T
D2 B0 B2 B4 B6 B8 T
D3 B1 B3 B5 B7 B9 T
D4 (Quad only) C0 C2 C4 C6 C8 T
D5 (Quad only) C1 C3 C5 C7 C9 T
D6 (Quad only) D0 D2 D4 D6 D8 T
D7 (Quad only) D1 D3 D5 D7 D9 T
Table 7-21 JMODE 1 (12-bit, 6/3/2 lanes, 8B/10B)
OCTET 0 1
NIBBLE 0 1 2 3
D0 A0[11:0] A1[11:8]
D1 A1[7:0]

Dual or Quad: B0[11:4]

Single: 0x00
D2 (Quad or Dual only) B0[3:0] B1[11:0]
D3 (Quad only) C0[11:0] C1[11:8]
D4 (Quad only) C1[7:0] D0[11:4]
D5 (Quad only) D0[3:0] D1[11:0]
Table 7-22 JMODE 2 (8-bit, 4/2/1 lanes, 8B/10B)
OCTET0
NIBBLE01
D0A0
D1 (Dual or Quad only)B0
D2 (Quad only)C0
D3 (Quad only)D0
Table 7-23 JMODE 3 (10-bit, 4/2/1 lanes, 8B/10B)
OCTET 0 1 2 3 4
NIBBLE 0 1 2 3 4 5 6 7 8 9
D0 A0 A1 A2 A3
D1 (Dual or Quad only) B0 B1 B2 B3
D2 (Quad only) C0 C1 C2 C3
D3 (Quad only) D0 D1 D2 D3
Table 7-24 JMODE 4 (12-bit, 3/2/1lanes, 64B/66B)
OCTET 0 1
NIBBLE 0 1 2 3
D0 A0[11:0] Quad or Dual: B0[11:8]
Single: 0x0
D1 (Dual or Quad only) B0[7:0] Quad: C0[11:4]
Dual: 0x00
D2 (Quad only) C0[3:0] D0[11:0]
Table 7-25 JMODE 5 (8-bit, 2/1/1 lanes, 64B/66B)
OCTET01
NIBBLE0123
D0A0Quad or Dual: B0
Single: 0x00
D1 (Quad Only)C0D0
Table 7-26 JMODE 6 (12-bit, 6/3/2 lanes, 64B/66B)
OCTET 0 1
NIBBLE 0 1 2 3
D0 A0[11:0] A1[11:8]
D1 A1[7:0] Dual or Quad: B0[11:4]
Single: 0x00
D2 (Dual or Quad only) B0[3:0] B1[11:0]
D3 (Quad only) C0[11:0] C1[11:8]
D4 (Quad only) C1[7:0] D0[11:4]
D5 (Quad only) D0[3:0] D1[11:0]
Table 7-27 JMODE 7 (8-bit, 4/2/1 lanes, 64B/66B)
OCTET0
NIBBLE01
D0A0
D1 (Dual or Quad only)B0
D2 (Quad only)C0
D3 (Quad only)D0
Table 7-28 JMODE 8 (12-bit, 4/2/1 lanes, 64B/66B)
OCTET 0 1 2
NIBBLE 0 1 2 3 4 5
D0 A0 A1
D1 (Dual or Quad only) B0 B1
D2 (Quad only) C0 C1
D3 (Quad only) D0 D1
Table 7-29 JMODE 9 (8-bit, 8/4/2lanes, 8B/10B)
OCTET0
NIBBLE01
D0A0
D1A1
D2 (Dual or Quad only)B0
D3 (Dual or Quad only)B1
D4 (Quad only)C0
D5 (Quad only)C1
D6 (Quad only)D0
D7 (Quad only)D1
Table 7-30 JMODE 10 (10-bit, 8/4/2 lanes, 8B/10B)
OCTET 0 1 2 3 4
NIBBLE 0 1 2 3 4 5 6 7 8 9
D0 A0 A2 A4 A6
D1 A1 A3 A5 A7
D2 (Dual or Quad only) B0 B2 B4 B6
D3 (Dual or Quad only) B1 B3 B5 B7
D4 (Quad only) C0 C2 C4 C6
D5 (Quad only) C1 C3 C5 C7
D6 (Quad only) D0 D2 D4 D6
D7 (Quad only) D1 D3 D5 D7
Table 7-31 JMODE 11 (12-bit, Dual/Single channel only, 8/4 lanes, 8B/10B)
OCTET 0 1 2 3 4 5 6 7
NIBBLE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 A0 A4 A8 A12 A16 T
D1 A1 A5 A9 A13 A17 T
D2 A2 A6 A10 A14 A18 T
D3 A3 A7 A11 A15 A19 T
D4 (Dual only) B0 B4 B8 B12 B16 T
D5 (Dual only) B1 B5 B9 B13 B17 T
D6 (Dual only) B2 B6 B10 B14 B18 T
D7 (Dual only) B3 B7 B11 B15 B19 T
Table 7-32 JMODE 12 (8-bit, Dual/Single channel only, 8/4 lanes, 64B/66B)
OCTET0
NIBBLE01
D0A0
D1A1
D2A2
D3A3
D4 (Dual only)B0
D5 (Dual only)B1
D6 (Dual only)B2
D7 (Dual only)B3
Table 7-33 JMODE 13 (10-bit, Dual/Single channel only, 8/4lanes, 8B/10B)
OCTET 0 1 2 3 4
NIBBLE 0 1 2 3 4 5 6 7 8 9
D0 A0 A4 A8 A12
D1 A1 A5 A9 A13
D2 A2 A6 A10 A14
D3 A3 A7 A11 A15
D4 (Dual only) B0 B4 B8 B12
D5 (Dual only) B1 B5 B9 B13
D6 (Dual only) B2 B6 B10 B14
D7 (Dual only) B3 B7 B11 B15
Table 7-34 JMODE 14 (12-bit, 8/4/2 lanes, 64B/66B)
OCTET 0 1 2
NIBBLE 0 1 2 3 4 5
D0 A0 A2
D1 A1 A3
D2 (Dual or Quad only) B0 B2
D3 (Dual or Quad only) B1 B3
D4 (Quad only) C0 C2
D5 (Quad only) C1 C3
D6 (Quad only) D0 D2
D7 (Quad only) D1 D3
Table 7-35 JMODE 15 (12-bit, Dual/Single channel only, 8/4 lanes, 64B/66B)
OCTET 0 1 2
NIBBLE 0 1 2 3 4 5
D0 A0 A4
D1 A1 A5
D2 A2 A6
D3 A3 A7
D4 (Dual only) B0 B4
D5 (Dual only) B1 B5
D6 (Dual only) B2 B6
D7 (Dual only) B3 B7
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