The clocking subsystem of the device has two input signals, device clock (CLK+, CLK–) and SYSREF (SYSREF+, SYSREF–). Within the clocking subsystem there is a noiseless aperture delay adjustment (t_AD adjust), a clock duty cycle corrector and a SYSREF capture block. Figure 7-2 describes the clocking subsystem.

Figure 7-2 Clocking Subsystem

The device clock is used as the sampling clock for the ADC core as well as the clocking for the digital processing and serializer outputs. Use a low-noise (low jitter) device clock to maintain high signal-to-noise ratio (SNR) within the ADC. In dual-channel mode, the analog input signal for each input is sampled on the rising edge of the device clock. In single-channel mode, both the rising and falling edges of the device clock are used to capture the analog signal to reduce the maximum clock rate required by the ADC. A noiseless aperture delay adjustment (t_AD adjust) allows the user to shift the sampling instance of the ADC in fine steps in order to synchronize multiple ADC12DJ5200-SPs or to fine-tune system latency. Duty cycle correction is implemented in the device to ease the requirements on the external device clock while maintaining high performance. Table 7-4 summarizes the device clock interface in dual-channel mode and single-channel mode.

SYSREF is a system timing reference used for JESD204C subclass-1 implementations of deterministic latency. SYSREF is used to achieve deterministic latency and for multi-device synchronization. SYSREF must be captured by the correct device clock edge in order to achieve repeatable latency and synchronization. The ADC12DJ5200-SP includes SYSREF windowing and automatic SYSREF calibration to ease the requirements on the external clocking circuits and to simplify the synchronization process. SYSREF can be implemented as a single pulse or as a periodic clock. In periodic implementations, SYSREF must be equal to, or an integer division of, the local multiframe clock frequency in 8B/10B encoding modes or the local extended multiblock clock frequency in 64B/66B encoding modes. Equation 2 is used to calculate valid SYSREF frequencies in 8B/10B encoding modes and Equation 3 in 64B/66B encoding modes.

Equation 2.

Equation 3.

where

• R and F are set by the JMODE setting (see Operating Modes)
• f_CLK is the device clock frequency (CLK±)
• K is the programmed multiframe length (see Operating Modes for valid K settings)
• E is the number of multiblocks in an extended multiblock.
• n is any positive integer