The ADC12DJ5200-SP can also be used as a single-channel ADC where the sampling rate is equal to two times the clock frequency (f_S = 2 × f_CLK) provided at the CLK+ and CLK– pins. This mode interleaves the two channels by sampling them out-of-phase and each channel samples separate analog inputs (INA± and INB±). The effective sampling rate is twice the device clock input (CLK±). This mode is useful for sampling the output of interleaved track-and-hold analog front-ends. This mode is chosen by setting JMODE to a single channel mode as described in Operating Modes and setting SINGLE_INPUT to use both INA± and INB± (see the input mux control register). The digital processing and JESD204C interface operate as if the device is in single-channel mode sampling only one of the inputs.