ZHCSQC0B June   2022  – March 2023 ADC12DJ5200-SP

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 描述
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: DC Specifications
    6. 6.6  Electrical Characteristics: Power Consumption
    7. 6.7  Electrical Characteristics: AC Specifications (Dual-Channel Mode)
    8. 6.8  Electrical Characteristics: AC Specifications (Single-Channel Mode)
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Device Comparison
      2. 7.3.2  Analog Inputs
        1. 7.3.2.1 Analog Input Protection
        2. 7.3.2.2 Full-Scale Voltage (VFS) Adjustment
        3. 7.3.2.3 Analog Input Offset Adjust
      3. 7.3.3  ADC Core
        1. 7.3.3.1 ADC Theory of Operation
        2. 7.3.3.2 ADC Core Calibration
        3. 7.3.3.3 Analog Reference Voltage
        4. 7.3.3.4 ADC Over-range Detection
        5. 7.3.3.5 Code Error Rate (CER)
      4. 7.3.4  Temperature Monitoring Diode
      5. 7.3.5  Timestamp
      6. 7.3.6  Clocking
        1. 7.3.6.1 Noiseless Aperture Delay Adjustment (tAD Adjust)
        2. 7.3.6.2 Aperture Delay Ramp Control (TAD_RAMP)
        3. 7.3.6.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          1. 7.3.6.3.1 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
          2. 7.3.6.3.2 Automatic SYSREF Calibration
      7. 7.3.7  Programmable FIR Filter (PFIR)
        1. 7.3.7.1 Dual Channel Equalization
        2. 7.3.7.2 Single Channel Equalization
        3. 7.3.7.3 Time Varying Filter
      8. 7.3.8  Digital Down Converters (DDC)
        1. 7.3.8.1 Rounding and Saturation
        2. 7.3.8.2 Numerically-Controlled Oscillator and Complex Mixer
          1. 7.3.8.2.1 NCO Fast Frequency Hopping (FFH)
          2. 7.3.8.2.2 NCO Selection
          3. 7.3.8.2.3 Basic NCO Frequency Setting Mode
          4. 7.3.8.2.4 Rational NCO Frequency Setting Mode
          5. 7.3.8.2.5 NCO Phase Offset Setting
          6. 7.3.8.2.6 NCO Phase Synchronization
        3. 7.3.8.3 Decimation Filters
        4. 7.3.8.4 Output Data Format
        5. 7.3.8.5 Decimation Settings
          1. 7.3.8.5.1 Decimation Factor
          2. 7.3.8.5.2 DDC Gain Boost
      9. 7.3.9  JESD204C Interface
        1. 7.3.9.1 Transport Layer
        2. 7.3.9.2 Scrambler
        3. 7.3.9.3 Link Layer
        4. 7.3.9.4 8B/10B Link Layer
          1. 7.3.9.4.1 Data Encoding (8B/10B)
          2. 7.3.9.4.2 Multiframes and the Local Multiframe Clock (LMFC)
          3. 7.3.9.4.3 Code Group Synchronization (CGS)
          4. 7.3.9.4.4 Initial Lane Alignment Sequence (ILAS)
          5. 7.3.9.4.5 Frame and Multiframe Monitoring
        5. 7.3.9.5 64B/66B Link Layer
          1. 7.3.9.5.1 64B/66B Encoding
          2. 7.3.9.5.2 Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)
          3. 7.3.9.5.3 Block, Multiblock and Extended Multiblock Alignment using Sync Header
            1. 7.3.9.5.3.1 Cyclic Redundancy Check (CRC) Mode
            2. 7.3.9.5.3.2 Forward Error Correction (FEC) Mode
          4. 7.3.9.5.4 Initial Lane Alignment
          5. 7.3.9.5.5 Block, Multiblock and Extended Multiblock Alignment Monitoring
        6. 7.3.9.6 Physical Layer
          1. 7.3.9.6.1 SerDes Pre-Emphasis
        7. 7.3.9.7 JESD204C Enable
        8. 7.3.9.8 Multi-Device Synchronization and Deterministic Latency
        9. 7.3.9.9 Operation in Subclass 0 Systems
      10. 7.3.10 Alarm Monitoring
        1. 7.3.10.1 Clock Upset Detection
        2. 7.3.10.2 FIFO Upset Detection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Dual-Channel Mode
      2. 7.4.2 Single-Channel Mode (DES Mode)
      3. 7.4.3 Dual-Input Single-Channel Mode (DUAL DES Mode)
      4. 7.4.4 JESD204C Modes
        1. 7.4.4.1 JESD204C Operating Modes Table
        2. 7.4.4.2 JESD204C Modes continued
        3. 7.4.4.3 JESD204C Transport Layer Data Formats
        4. 7.4.4.4 64B/66B Sync Header Stream Configuration
      5. 7.4.5 Power-Down Modes
      6. 7.4.6 Test Modes
        1. 7.4.6.1 Serializer Test-Mode Details
        2. 7.4.6.2 PRBS Test Modes
        3. 7.4.6.3 Clock Pattern Mode
        4. 7.4.6.4 Ramp Test Mode
        5. 7.4.6.5 Short and Long Transport Test Mode
          1. 7.4.6.5.1 Short Transport Test Pattern
        6. 7.4.6.6 D21.5 Test Mode
        7. 7.4.6.7 K28.5 Test Mode
        8. 7.4.6.8 Repeated ILA Test Mode
        9. 7.4.6.9 Modified RPAT Test Mode
      7. 7.4.7 Calibration Modes and Trimming
        1. 7.4.7.1 Foreground Calibration Mode
        2. 7.4.7.2 Background Calibration Mode
        3. 7.4.7.3 Low-Power Background Calibration (LPBG) Mode
      8. 7.4.8 Offset Calibration
      9. 7.4.9 Trimming
    5. 7.5 Programming
      1. 7.5.1 Using the Serial Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 Streaming Mode
    6. 7.6 SPI Register Map
  8. 8 Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Wideband RF Sampling Receiver
        1. 8.2.1.1 Design Requirements
          1. 8.2.1.1.1 Input Signal Path
          2. 8.2.1.1.2 Clocking
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Calculating Values of AC-Coupling Capacitors
      2. 8.2.2 Reconfigurable Dual-Channel 5-GSPS or Single-Channel 10-Gsps Oscilloscope
        1. 8.2.2.1 Design Requirements
          1. 8.2.2.1.1 Input Signal Path
          2. 8.2.2.1.2 Clocking
          3. 8.2.2.1.3 ADC12DJ5200-SP
    3. 8.3 Initialization Set Up
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 Power Sequencing
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 143
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 静电放电警告
    7. 9.7 术语表
  10. 10Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • ALR|144
散热焊盘机械数据 (封装 | 引脚)
订购信息
8.2.2.1.3 ADC12DJ5200-SP

ADC12DJ5200-SP has a number of features that make it a great fit for oscilloscope applications. The low code-error rate (CER) eliminates concerns about undesired time domain glitches or sparkle codes. The low CER makes the device a perfect fit for long-duration transient detection measurements and reduces the probability of false triggers. The input common-mode voltage of 0 V allows the driving amplifiers to use equal split power supplies that center the amplifier output common-mode voltage at 0 V and eliminates the need for common-mode voltage shifting before the ADC inputs. The high input bandwidth of the device simplifies the design of the driving amplifier circuit and antialiasing, low-pass filter. The use of dual-edge sampling (DES) in single-channel mode eliminates the need to change the clock frequency when switching between dual- and single-channel modes and simplifies synchronization by relaxing the setup and hold timing requirements of SYSREF. The tAD adjust circuit allows the user to time-align the sampling instances of multiple ADC12DJ5200-SP devices or to set the ideal sampling point of a front-end track and hold (T&H) amplifier.
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