ZHCSQC0B June 2022 – March 2023 ADC12DJ5200-SP
PRODUCTION DATA
The ADC12DJ5200-SP clock inputs must be AC-coupled to the device to ensure rated performance. The clock source must have extremely low jitter (integrated phase noise) to enable rated performance. Recommended clock synthesizers include LMX2594 and LMX2572.
The JESD204C data converter system (ADC plus logic device) requires additional SYSREF and device clocks. LMK04832, LMK04828, LMK04826, and LMK04821 devices are suitable to generate these clocks. Depending on the ADC clock frequency and jitter requirements, this device can also be used as the system clock synthesizer or as a device clock and SYSREF distribution device when multiple ADC12DJ5200-SP devices are used in a system. For clock frequencies higher than 3.2 GHz, LMX2594 and LMX2572 can supply both the device clock and SYSREF from a single device as demonstrated in Figure 8-1.