ZHCSQC0B June   2022  – March 2023 ADC12DJ5200-SP

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 描述
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: DC Specifications
    6. 6.6  Electrical Characteristics: Power Consumption
    7. 6.7  Electrical Characteristics: AC Specifications (Dual-Channel Mode)
    8. 6.8  Electrical Characteristics: AC Specifications (Single-Channel Mode)
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Device Comparison
      2. 7.3.2  Analog Inputs
        1. 7.3.2.1 Analog Input Protection
        2. 7.3.2.2 Full-Scale Voltage (VFS) Adjustment
        3. 7.3.2.3 Analog Input Offset Adjust
      3. 7.3.3  ADC Core
        1. 7.3.3.1 ADC Theory of Operation
        2. 7.3.3.2 ADC Core Calibration
        3. 7.3.3.3 Analog Reference Voltage
        4. 7.3.3.4 ADC Over-range Detection
        5. 7.3.3.5 Code Error Rate (CER)
      4. 7.3.4  Temperature Monitoring Diode
      5. 7.3.5  Timestamp
      6. 7.3.6  Clocking
        1. 7.3.6.1 Noiseless Aperture Delay Adjustment (tAD Adjust)
        2. 7.3.6.2 Aperture Delay Ramp Control (TAD_RAMP)
        3. 7.3.6.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          1. 7.3.6.3.1 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
          2. 7.3.6.3.2 Automatic SYSREF Calibration
      7. 7.3.7  Programmable FIR Filter (PFIR)
        1. 7.3.7.1 Dual Channel Equalization
        2. 7.3.7.2 Single Channel Equalization
        3. 7.3.7.3 Time Varying Filter
      8. 7.3.8  Digital Down Converters (DDC)
        1. 7.3.8.1 Rounding and Saturation
        2. 7.3.8.2 Numerically-Controlled Oscillator and Complex Mixer
          1. 7.3.8.2.1 NCO Fast Frequency Hopping (FFH)
          2. 7.3.8.2.2 NCO Selection
          3. 7.3.8.2.3 Basic NCO Frequency Setting Mode
          4. 7.3.8.2.4 Rational NCO Frequency Setting Mode
          5. 7.3.8.2.5 NCO Phase Offset Setting
          6. 7.3.8.2.6 NCO Phase Synchronization
        3. 7.3.8.3 Decimation Filters
        4. 7.3.8.4 Output Data Format
        5. 7.3.8.5 Decimation Settings
          1. 7.3.8.5.1 Decimation Factor
          2. 7.3.8.5.2 DDC Gain Boost
      9. 7.3.9  JESD204C Interface
        1. 7.3.9.1 Transport Layer
        2. 7.3.9.2 Scrambler
        3. 7.3.9.3 Link Layer
        4. 7.3.9.4 8B/10B Link Layer
          1. 7.3.9.4.1 Data Encoding (8B/10B)
          2. 7.3.9.4.2 Multiframes and the Local Multiframe Clock (LMFC)
          3. 7.3.9.4.3 Code Group Synchronization (CGS)
          4. 7.3.9.4.4 Initial Lane Alignment Sequence (ILAS)
          5. 7.3.9.4.5 Frame and Multiframe Monitoring
        5. 7.3.9.5 64B/66B Link Layer
          1. 7.3.9.5.1 64B/66B Encoding
          2. 7.3.9.5.2 Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)
          3. 7.3.9.5.3 Block, Multiblock and Extended Multiblock Alignment using Sync Header
            1. 7.3.9.5.3.1 Cyclic Redundancy Check (CRC) Mode
            2. 7.3.9.5.3.2 Forward Error Correction (FEC) Mode
          4. 7.3.9.5.4 Initial Lane Alignment
          5. 7.3.9.5.5 Block, Multiblock and Extended Multiblock Alignment Monitoring
        6. 7.3.9.6 Physical Layer
          1. 7.3.9.6.1 SerDes Pre-Emphasis
        7. 7.3.9.7 JESD204C Enable
        8. 7.3.9.8 Multi-Device Synchronization and Deterministic Latency
        9. 7.3.9.9 Operation in Subclass 0 Systems
      10. 7.3.10 Alarm Monitoring
        1. 7.3.10.1 Clock Upset Detection
        2. 7.3.10.2 FIFO Upset Detection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Dual-Channel Mode
      2. 7.4.2 Single-Channel Mode (DES Mode)
      3. 7.4.3 Dual-Input Single-Channel Mode (DUAL DES Mode)
      4. 7.4.4 JESD204C Modes
        1. 7.4.4.1 JESD204C Operating Modes Table
        2. 7.4.4.2 JESD204C Modes continued
        3. 7.4.4.3 JESD204C Transport Layer Data Formats
        4. 7.4.4.4 64B/66B Sync Header Stream Configuration
      5. 7.4.5 Power-Down Modes
      6. 7.4.6 Test Modes
        1. 7.4.6.1 Serializer Test-Mode Details
        2. 7.4.6.2 PRBS Test Modes
        3. 7.4.6.3 Clock Pattern Mode
        4. 7.4.6.4 Ramp Test Mode
        5. 7.4.6.5 Short and Long Transport Test Mode
          1. 7.4.6.5.1 Short Transport Test Pattern
        6. 7.4.6.6 D21.5 Test Mode
        7. 7.4.6.7 K28.5 Test Mode
        8. 7.4.6.8 Repeated ILA Test Mode
        9. 7.4.6.9 Modified RPAT Test Mode
      7. 7.4.7 Calibration Modes and Trimming
        1. 7.4.7.1 Foreground Calibration Mode
        2. 7.4.7.2 Background Calibration Mode
        3. 7.4.7.3 Low-Power Background Calibration (LPBG) Mode
      8. 7.4.8 Offset Calibration
      9. 7.4.9 Trimming
    5. 7.5 Programming
      1. 7.5.1 Using the Serial Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 Streaming Mode
    6. 7.6 SPI Register Map
  8. 8 Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Wideband RF Sampling Receiver
        1. 8.2.1.1 Design Requirements
          1. 8.2.1.1.1 Input Signal Path
          2. 8.2.1.1.2 Clocking
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Calculating Values of AC-Coupling Capacitors
      2. 8.2.2 Reconfigurable Dual-Channel 5-GSPS or Single-Channel 10-Gsps Oscilloscope
        1. 8.2.2.1 Design Requirements
          1. 8.2.2.1.1 Input Signal Path
          2. 8.2.2.1.2 Clocking
          3. 8.2.2.1.3 ADC12DJ5200-SP
    3. 8.3 Initialization Set Up
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 Power Sequencing
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 143
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 静电放电警告
    7. 9.7 术语表
  10. 10Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • ALR|144
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.4.4.3 JESD204C Transport Layer Data Formats

Output data are formatted in a specific optimized fashion for each JMODE setting based on the transport layer settings for that JMODE. When the DDC is not used (decimation = 1) the 12-bit offset binary values are mapped into octets. For the DDC mode, the 16-bit values (15-bit complex data plus 1 overrange bit) are mapped into octets. The following tables show the specific mapping formats for a single frame for each JMODE. The symbol definitions used in the JMODE tables is provided in Table 7-25. In all mappings the tail bits (T) are 0 (zero). All samples are formatted as MSB first, LSB last.

Table 7-25 JMODE Table Symbol Definitions
NOTATIONMODEDESCRIPTION
S[n]Single channel, DDC bypassedSample n from ADC in single channel mode when DDC is bypassed
A[n]Dual channel, DDC bypassedSample n from channel A in dual channel mode when DDC is bypassed
B[n]Dual channel, DDC bypassedSample n from channel A in dual channel mode when DDC is bypassed
T—Tail bits, always set to 0
AI[n], AQ[n]Dual channel, DDC enabledComplex I/Q sample n from DDC A in dual channel mode
BI[n], BQ[n]Dual channel, DDC enabledComplex I/Q sample n from DDC B in dual channel mode
ORA0[n]Dual channel, DDC enabledOverrange flag for channel A, set high if channel A sample n exceeds overrange threshold 0 (OVR_T0)
ORA1[n]Dual channel, DDC enabledOverrange flag for channel A, set high if channel A sample n exceeds overrange threshold 1 (OVR_T1)
ORB0[n]Dual channel, DDC enabledOverrange flag for channel B, set high if channel B sample n exceeds overrange threshold 0 (OVR_T0)
ORB1[n]Dual channel, DDC enabledOverrange flag for channel B, set high if channel B sample n exceeds overrange threshold 1 (OVR_T1)
I[n], Q[n]Single channel, DDC enabledComplex I/Q sample n from the DDC in single channel mode
OR0[n]Single channel, DDC enabledOverrange flag, set high if sample n exceeds overrange threshold 0 (OVR_T0)
OR1[n]Single channel, DDC enabledOverrange flag, set high if sample n exceeds overrange threshold 1 (OVR_T1)
Table 7-26 JMODE 0 (12-bit, Single Channel, DDC Bypass, 8 lanes)
OCTET01234567
NIBBLE0123456789101112131415
DA0S[0]S[8]S[16]S[24]S[32]T
DA1S[2]S[10]S[18]S[26]S[34]T
DA2S[4]S[12]S[20]S[28]S[36]T
DA3S[6]S[14]S[22]S[30]S[38]T
DB0S[1]S[9]S[17]S[25]S[33]T
DB1S[3]S[11]S[19]S[27]S[35]T
DB2S[5]S[13]S[21]S[29]S[37]T
DB3S[7]S[15]S[23]S[31]S[39]T

Table 7-26 also applies to JMODE 30.

Table 7-27 JMODE 1 (12-bit, Single Channel, DDC Bypass, 16 lanes)
OCTET01234567
NIBBLE0123456789101112131415
DA0S[0]S[16]S[32]S[48]S[64]T
DA1S[2]S[18]S[34]S[50]S[66]T
DA2S[4]S[20]S[36]S[52]S[68]T
DA3S[6]S[22]S[38]S[54]S[70]T
DA4S[8]S[24]S[40]S[56]S[72]T
DA5S[10]S[26]S[42]S[58]S[74]T
DA6S[12]S[28]S[44]S[60]S[76]T
DA7S[14]S[30]S[46]S[62]S[78]T
DB0S[1]S[17]S[33]S[49]S[65]T
DB1S[3]S[19]S[35]S[51]S[67]T
DB2S[5]S[21]S[37]S[53]S[69]T
DB3S[7]S[23]S[39]S[55]S[71]T
DB4S[9]S[25]S[41]S[57]S[73]T
DB5S[11]S[27]S[43]S[59]S[75]T
DB6S[13]S[29]S[45]S[61]S[77]T
DB7S[15]S[31]S[47]S[63]S[79]T

Table 7-27 also applies to JMODE 40.

Table 7-28 JMODE 2 (12-Bit, Dual Channel, DDC Bypass, 8 Lanes)
OCTET01234567
NIBBLE0123456789101112131415
DA0A[0]A[4]A[8]A[12]A[16]T
DA1A[1]A[5]A[9]A[13]A[17]T
DA2A[2]A[6]A[10]A[14]A[18]T
DA3A[3]A[7]A[11]A[15]A[19]T
DB0B[0]B[4]B[8]B[12]B[16]T
DB1B[1]B[5]B[9]B[13]B[17]T
DB2B[2]B[6]B[10]B[14]B[18]T
DB3B[3]B[7]B[11]B[15]B[19]T

Table 7-28 also applies to JMODE 31.

Table 7-29 JMODE 3 (12-Bit, Dual Channel, DDC Bypass, 16 Lanes)
OCTET01234567
NIBBLE0123456789101112131415
DA0A[0]A[8]A[16]A[24]A[32]T
DA1A[1]A[9]A[17]A[25]A[33]T
DA2A[2]A[10]A[18]A[26]A[34]T
DA3A[3]A[11]A[19]A[27]A[35]T
DA4A[4]A[12]A[20]A[28]A[36]T
DA5A[5]A[13]A[21]A[29]A[37]T
DA6A[6]A[14]A[22]A[30]A[38]T
DA7A[7]A[15]A[23]A[31]A[39]T
DB0B[0]B[8]B[16]B[24]B[32]T
DB1B[1]B[9]B[17]B[25]B[33]T
DB2B[2]B[10]B[18]B[26]B[34]T
DB3B[3]B[11]B[19]B[27]B[35]T
DB4B[4]B[12]B[20]B[28]B[36]T
DB5B[5]B[13]B[21]B[29]B[37]T
DB6B[6]B[14]B[22]B[30]B[38]T
DB7B[7]B[15]B[23]B[31]B[39]T

Table 7-29 also applies to JMODE 41.

Table 7-30 JMODE 5 (8-bit, Single Channel, 8 Lanes)
OCTET0
NIBBLE01
DA0S[0]
DA1S[2]
DA2S[4]
DA3S[6]
DB0S[1]
DB1S[3]
DB2S[5]
DB3S[7]

Table 7-30 also applies to JMODE 44.

Table 7-31 JMODE 6 (8-bit, Single Channel, 16 Lanes)
OCTET0
NIBBLE01
DA0S[0]
DA1S[2]
DA2S[4]
DA3S[6]
DA4S[8]
DA5S[10]
DA6S[12]
DA7S[14]
DB0S[1]
DB1S[3]
DB2S[5]
DB3S[7]
DB4S[9]
DB5S[11]
DB6S[13]
DB7S[15]

Table 7-31 also applies to JMODE 50.

Table 7-32 JMODE 7 (8-bit, Dual Channel, 8 Lanes)
OCTET0
NIBBLE01
DA0A[0]
DA1A[1]
DA2A[2]
DA3A[3]
DB0B[0]
DB1B[1]
DB2B[2]
DB3B[3]

Table 7-32 also applies to JMODE 45.

Table 7-33 JMODE 8 (8-bit, Dual Channel, 16 Lanes)
OCTET0
NIBBLE01
DA0A[0]
DA1A[1]
DA2A[2]
DA3A[3]
DA4A[4]
DA5A[5]
DA6A[6]
DA7A[7]
DB0B[0]
DB1B[1]
DB2B[2]
DB3B[3]
DB4B[4]
DB5B[5]
DB6B[6]
DB7B[7]

Table 7-33 also applies to JMODE 51.

Table 7-34 JMODE 10 (15-bit, Dual Channel, Decimate-by-4, 4 lanes)
OCTET01
NIBBLE0123
DA0AI[0], ORA0[0]
DA1AQ[0], ORA1[0]
DB0BI[0], ORB0[0]
DB1BQ[0], ORB1[0]

Table 7-34 also applies to JMODE 37.

Table 7-35 JMODE 11 (15-bit, Dual Channel, Decimate-by-4, 8 lanes)
OCTET01
NIBBLE0123
DA0AI[0], ORA0[0]
DA1AI[1], ORA0[1]
DA2AQ[0], ORA1[0]
DA3AQ[1], ORA1[1]
DB0BI[0], ORB0[0]
DB1BI[1], ORB0[1]
DB2BQ[0], ORB1[0]
DB3BQ[1], ORB1[1]

Table 7-35 also applies to JMODE 47.

Table 7-36 JMODE 12 (15-bit, Dual Channel, Decimate-by-4, 16 lanes)
OCTET01
NIBBLE0123
DA0AI[0], ORA0[0]
DA1AI[1], ORA0[1]
DA2AI[2], ORA0[2]
DA3AI[3], ORA0[3]
DA4AQ[0], ORA1[0]
DA5AQ[1], ORA1[1]
DA6AQ[2], ORA1[2]
DA7AQ[3], ORA1[3]
DB0BI[0], ORB0[0]
DB1BI[1], ORB0[1]
DB2BI[2], ORB0[2]
DB3BI[3], ORB0[3]
DB4BQ[0], ORB1[0]
DB5BQ[1], ORB1[1]
DB6BQ[2], ORB1[2]
DB7BQ[3], ORB1[3]

Table 7-36 also applies to JMODE 53.

Table 7-37 JMODE 13 (15-bit, Dual Channel, Decimate-by-8, 2 lanes)
OCTET0123
NIBBLE01234567
DA0AI[0], ORA0[0]AQ[0], ORA1[0]
DB0BI[0], ORB0[0]BQ[0], ORB1[0]

Table 7-37 also applies to JMODE 39,JMODE 56, JMODE 59, JMODE 66 and JMODE 68.

Table 7-38 JMODE 14 (15-bit, Dual Channel, Decimate-by-8, 4 lanes)
OCTET01
NIBBLE0123
DA0AI[0], ORA0[0]
DA1AQ[0], ORA1[0]
DB0BI[0], ORB0[0]
DB1BQ[0], ORB1[0]

Table 7-38 also applies to JMODE 49, JMODE 57, JMODE 60 and JMODE 67.

Table 7-39 JMODE 15 (15-bit, Dual Channel, Decimate-by-8, 8 lanes)
OCTET01
NIBBLE0123
DA0AI[0], ORA0[0]
DA1AI[1], ORA0[1]
DA2AQ[0], ORA1[0]
DA3AQ[1], ORA1[1]
DB0BI[0], ORB0[0]
DB1BI[1], ORB0[1]
DB2BQ[0], ORB1[0]
DB3BQ[1], ORB1[1]

Table 7-39 also applies to JMODE 55 and JMODE 58.

Table 7-40 JMODE 16 (15-bit, Dual Channel, Decimate-by-8, 16 lanes)
OCTET01
NIBBLE0123
DA0AI[0], ORA0[0]
DA1AI[1], ORA0[1]
DA2AI[2], ORA0[2]
DA3AI[3], ORA0[3]
DA4AQ[0], ORA1[0]
DA5AQ[1], ORA1[1]
DA6AQ[2], ORA1[2]
DA7AQ[3], ORA1[3]
DB0BI[0], ORB0[0]
DB1BI[1], ORB0[1]
DB2BI[2], ORB0[2]
DB3BI[3], ORB0[3]
DB4BQ[0], ORB1[0]
DB5BQ[1], ORB1[1]
DB6BQ[2], ORB1[2]
DB7BQ[3], ORB1[3]
Table 7-41 JMODE 19 (12-bit, Single Channel, DDC Bypass, 12 lanes)
OCTET01
NIBBLE0123
DA0S[0][11:0]S[2][11:8]
DA1S[2][7:0]S[4][11:4]
DA2S[4][3:0]S[6][11:0]
DA3S[8][11:0]S[10][11:8]
DA4S[10][7:0]S[12][11:4]
DA5S[12][3:0]S[14][11:0]
DB0S[1][11:0]S[3][11:8]
DB1S[3][7:0]S[5][11:4]
DB2S[5][3:0]S[7][11:0]
DB3S[9][11:0]S[11][11:8]
DB4S[11][7:0]S[13][11:4]
DB5S[13][3:0]S[15][11:0]

Table 7-41 also applies to JMODE 42.

Table 7-42 JMODE 20 (12-bit, Dual Channel, DDC Bypass, 12 lanes)
OCTET01
NIBBLE0123
DA0A[0][11:0]A[1][11:8]
DA1A[1][7:0]A[2][11:4]
DA2A[2][3:0]A[3][11:0]
DA3A[4][11:0]A[5][11:8]
DA4A[5][7:0]A[6][11:4]
DA5A[6][3:0]A[7][11:0]
DB0B[0][11:0]B[1][11:8]
DB1B[1][7:0]B[2][11:4]
DB2B[2][3:0]B[3][11:0]
DB3B[4][11:0]B[5][11:8]
DB4B[5][7:0]B[6][11:4]
DB5B[6][3:0]B[7][11:0]

Table 7-42 also applies to JMODE 43.

Table 7-43 JMODE 21 (15-bit, Single Channel, Decimate-by-4, 4 lanes)
OCTET0
NIBBLE01
DA0I[0], OR0[0]
DA1I[1], OR0[1]
DB0Q[0], OR1[0]
DB1Q[1], OR1[1]

Table 7-43 also applies to JMODE 36.

Table 7-44 JMODE 22 (15-bit, Single Channel, Decimate-by-4, 8 lanes)
OCTET0
NIBBLE01
DA0I[0], OR0[0]
DA1I[1], OR0[1]
DA2I[2], OR0[2]
DA3I[3], OR0[3]
DB0Q[0], OR1[0]
DB1Q[1], OR1[1]
DB2Q[2], OR1[2]
DB3Q[3], OR1[3]

Table 7-44 also applies to JMODE 46.

Table 7-45 JMODE 23 (15-bit, Single Channel, Decimate-by-8, 2 lanes)
OCTET0
NIBBLE01
DA0I[0], OR0[0]
DB0Q[0], OR1[0]

Table 7-45 also applies to JMODE 38, JMODE 61, JMODE 64, JMODE 69 and JMODE 71.

Table 7-46 JMODE 24 (15-bit, Single Channel, Decimate-by-8, 4 lanes)
OCTET0
NIBBLE01
DA0I[0], OR0[0]
DA1I[1], OR0[1]
DB0Q[0], OR1[0]
DB1Q[1], OR1[1]

Table 7-46 also applies to JMODE 48, JMODE 62, JMODE 65 and JMODE 70.

Table 7-47 JMODE 25 (15-bit, Single Channel, Decimate-by-4, 16 lanes)
OCTET01
NIBBLE0123
DA0I[0], OR0[0]
DA1I[1], OR0[0]
DA2I[2], OR0[1]
DA3I[3], OR0[1]
DA4I[4], OR0[2]
DA5I[5], OR0[2]
DA6I[6], OR0[3]
DA7I[7], OR0[3]
DB0Q[0], OR1[0]
DB1Q[1], OR1[0]
DB2Q[2], OR1[1]
DB3Q[3], OR1[1]
DB4Q[4], OR1[2]
DB5Q[5], OR1[2]
DB6Q[6], OR1[3]
DB7Q[7], OR1[3]

Table 7-47 also applies to JMODE 52.

Table 7-48 JMODE 26 (15-bit, Single Channel, Decimate-by-8, 8 lanes)
OCTET01
NIBBLE0123
DA0I[0], OR0[0]
DA1I[1], OR0[1]
DA2I[2], OR0[2]
DA3I[3], OR0[3]
DB0Q[0], OR1[0]
DB1Q[1], OR1[1]
DB2Q[2], OR1[2]
DB3Q[3], OR1[3]

Table 7-48 also applies to JMODE 54 and JMODE 63.

Table 7-49 JMODE 27 (15-bit, Single Channel, Decimate-by-8, 16 lanes)
OCTET01
NIBBLE0123
DA0I[0], OR0[0]
DA1I[1], OR0[1]
DA2I[2], OR0[2]
DA3I[3], OR0[3]
DA4I[4], OR0[4]
DA5I[5], OR0[5]
DA6I[6], OR0[6]
DA7I[7], OR0[7]
DB0Q[0], OR1[0]
DB1Q[1], OR1[1]
DB2Q[2], OR1[2]
DB3Q[3], OR1[3]
DB4Q[4], OR1[4]
DB5Q[5], OR1[5]
DB6Q[6], OR1[6]
DB7Q[7], OR1[7]
Table 7-50 JMODE 32 (12-bit, Single Channel, DDC Bypass, 6 lanes)
OCTET01
NIBBLE0123
DA0S[0][11:0]S[2][11:8]
DA1S[2][7:0]S[4][11:4]
DA2S[4][3:0]S[6][11:0]
DB0S[1][11:0]S[3][11:8]
DB1S[3][7:0]S[5][11:4]
DB2S[5][3:0]S[7][11:0]
Table 7-51 JMODE 33 (12-bit, Dual Channel, DDC Bypass, 6 lanes)
OCTET01
NIBBLE0123
DA0A[0][11:0]A[1][11:8]
DA1A[1][7:0]A[2][11:4]
DA2A[2][3:0]A[3][11:0]
DB0B[0][11:0]B[1][11:8]
DB1B[1][7:0]B[2][11:4]
DB2B[2][3:0]B[3][11:0]
Table 7-52 JMODE 34 (8-bit, Single Channel, 4 lanes)
OCTET0
NIBBLE01
DA0S[0]
DA1S[2]
DB0S[1]
DB1S[3]
Table 7-53 JMODE 35 (8-bit, Dual Channel, 4 lanes)
OCTET0
NIBBLE01
DA0A[0]
DA1A[1]
DB0B[0]
DB1B[1]
Table 7-54 JMODE 37 (15-bit, Dual Channel, Decimate-by-4, 4 lanes)
OCTET01
NIBBLE0123
DA0AI[0], ORA0[0]
DA1AQ[0], ORA1[0]
DB0BI[0], ORB0[0]
DB1BQ[0], ORB1[0]
Table 7-55 JMODE 38 (15-bit, Single Channel, Decimate-by-8, 2 lanes)
OCTET0
NIBBLE01
DA0I[0], OR0[0]
DB0Q[0], OR1[0]
Table 7-56 JMODE 39 (15-bit, Dual Channel, Decimate-by-8, 2 lanes)
OCTET0123
NIBBLE01234567
DA0AI[0], ORA0[0]AQ[0], ORA1[0]
DB0BI[0], ORB0[0]BQ[0], ORB1[0]
Table 7-57 JMODE 56 (15-bit, Dual Channel, Decimate-by-16, 2 lanes)
OCTET0123
NIBBLE01234567
DA0AI[0], ORA0[0]AQ[0], ORA1[0]
DB0BI[0], ORB0[0]BQ[0], ORB1[0]
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