ZHCSQC0B June   2022  – March 2023 ADC12DJ5200-SP

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 描述
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: DC Specifications
    6. 6.6  Electrical Characteristics: Power Consumption
    7. 6.7  Electrical Characteristics: AC Specifications (Dual-Channel Mode)
    8. 6.8  Electrical Characteristics: AC Specifications (Single-Channel Mode)
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Device Comparison
      2. 7.3.2  Analog Inputs
        1. 7.3.2.1 Analog Input Protection
        2. 7.3.2.2 Full-Scale Voltage (VFS) Adjustment
        3. 7.3.2.3 Analog Input Offset Adjust
      3. 7.3.3  ADC Core
        1. 7.3.3.1 ADC Theory of Operation
        2. 7.3.3.2 ADC Core Calibration
        3. 7.3.3.3 Analog Reference Voltage
        4. 7.3.3.4 ADC Over-range Detection
        5. 7.3.3.5 Code Error Rate (CER)
      4. 7.3.4  Temperature Monitoring Diode
      5. 7.3.5  Timestamp
      6. 7.3.6  Clocking
        1. 7.3.6.1 Noiseless Aperture Delay Adjustment (tAD Adjust)
        2. 7.3.6.2 Aperture Delay Ramp Control (TAD_RAMP)
        3. 7.3.6.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          1. 7.3.6.3.1 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
          2. 7.3.6.3.2 Automatic SYSREF Calibration
      7. 7.3.7  Programmable FIR Filter (PFIR)
        1. 7.3.7.1 Dual Channel Equalization
        2. 7.3.7.2 Single Channel Equalization
        3. 7.3.7.3 Time Varying Filter
      8. 7.3.8  Digital Down Converters (DDC)
        1. 7.3.8.1 Rounding and Saturation
        2. 7.3.8.2 Numerically-Controlled Oscillator and Complex Mixer
          1. 7.3.8.2.1 NCO Fast Frequency Hopping (FFH)
          2. 7.3.8.2.2 NCO Selection
          3. 7.3.8.2.3 Basic NCO Frequency Setting Mode
          4. 7.3.8.2.4 Rational NCO Frequency Setting Mode
          5. 7.3.8.2.5 NCO Phase Offset Setting
          6. 7.3.8.2.6 NCO Phase Synchronization
        3. 7.3.8.3 Decimation Filters
        4. 7.3.8.4 Output Data Format
        5. 7.3.8.5 Decimation Settings
          1. 7.3.8.5.1 Decimation Factor
          2. 7.3.8.5.2 DDC Gain Boost
      9. 7.3.9  JESD204C Interface
        1. 7.3.9.1 Transport Layer
        2. 7.3.9.2 Scrambler
        3. 7.3.9.3 Link Layer
        4. 7.3.9.4 8B/10B Link Layer
          1. 7.3.9.4.1 Data Encoding (8B/10B)
          2. 7.3.9.4.2 Multiframes and the Local Multiframe Clock (LMFC)
          3. 7.3.9.4.3 Code Group Synchronization (CGS)
          4. 7.3.9.4.4 Initial Lane Alignment Sequence (ILAS)
          5. 7.3.9.4.5 Frame and Multiframe Monitoring
        5. 7.3.9.5 64B/66B Link Layer
          1. 7.3.9.5.1 64B/66B Encoding
          2. 7.3.9.5.2 Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)
          3. 7.3.9.5.3 Block, Multiblock and Extended Multiblock Alignment using Sync Header
            1. 7.3.9.5.3.1 Cyclic Redundancy Check (CRC) Mode
            2. 7.3.9.5.3.2 Forward Error Correction (FEC) Mode
          4. 7.3.9.5.4 Initial Lane Alignment
          5. 7.3.9.5.5 Block, Multiblock and Extended Multiblock Alignment Monitoring
        6. 7.3.9.6 Physical Layer
          1. 7.3.9.6.1 SerDes Pre-Emphasis
        7. 7.3.9.7 JESD204C Enable
        8. 7.3.9.8 Multi-Device Synchronization and Deterministic Latency
        9. 7.3.9.9 Operation in Subclass 0 Systems
      10. 7.3.10 Alarm Monitoring
        1. 7.3.10.1 Clock Upset Detection
        2. 7.3.10.2 FIFO Upset Detection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Dual-Channel Mode
      2. 7.4.2 Single-Channel Mode (DES Mode)
      3. 7.4.3 Dual-Input Single-Channel Mode (DUAL DES Mode)
      4. 7.4.4 JESD204C Modes
        1. 7.4.4.1 JESD204C Operating Modes Table
        2. 7.4.4.2 JESD204C Modes continued
        3. 7.4.4.3 JESD204C Transport Layer Data Formats
        4. 7.4.4.4 64B/66B Sync Header Stream Configuration
      5. 7.4.5 Power-Down Modes
      6. 7.4.6 Test Modes
        1. 7.4.6.1 Serializer Test-Mode Details
        2. 7.4.6.2 PRBS Test Modes
        3. 7.4.6.3 Clock Pattern Mode
        4. 7.4.6.4 Ramp Test Mode
        5. 7.4.6.5 Short and Long Transport Test Mode
          1. 7.4.6.5.1 Short Transport Test Pattern
        6. 7.4.6.6 D21.5 Test Mode
        7. 7.4.6.7 K28.5 Test Mode
        8. 7.4.6.8 Repeated ILA Test Mode
        9. 7.4.6.9 Modified RPAT Test Mode
      7. 7.4.7 Calibration Modes and Trimming
        1. 7.4.7.1 Foreground Calibration Mode
        2. 7.4.7.2 Background Calibration Mode
        3. 7.4.7.3 Low-Power Background Calibration (LPBG) Mode
      8. 7.4.8 Offset Calibration
      9. 7.4.9 Trimming
    5. 7.5 Programming
      1. 7.5.1 Using the Serial Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 Streaming Mode
    6. 7.6 SPI Register Map
  8. 8 Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Wideband RF Sampling Receiver
        1. 8.2.1.1 Design Requirements
          1. 8.2.1.1.1 Input Signal Path
          2. 8.2.1.1.2 Clocking
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Calculating Values of AC-Coupling Capacitors
      2. 8.2.2 Reconfigurable Dual-Channel 5-GSPS or Single-Channel 10-Gsps Oscilloscope
        1. 8.2.2.1 Design Requirements
          1. 8.2.2.1.1 Input Signal Path
          2. 8.2.2.1.2 Clocking
          3. 8.2.2.1.3 ADC12DJ5200-SP
    3. 8.3 Initialization Set Up
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 Power Sequencing
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 143
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 静电放电警告
    7. 9.7 术语表
  10. 10Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • ALR|144
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.7 Electrical Characteristics: AC Specifications (Dual-Channel Mode)

typical values at TJ = 50°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, fIN = 347 MHz, AIN = –1 dBFS, fCLK = 5.12 GHz, filtered 1-VPP sine-wave clock, JMODE = 3, Dither enabled with default settings, VA11, VD11 and VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over the operating junction temperature range provided in the Recommended Operating Conditions table
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
FPBW Full-power input bandwidth (–3 dB)(1) Foreground calibration 8.1 GHz
Background calibration 8.1
XTALK Channel-to-channel crosstalk Aggressor = 1 GHz, –1 dBFS –77 dB
Aggressor = 3 GHz, –1 dBFS –71
Aggressor = 6 GHz, –1 dBFS –63
CER Code error rate Maximum CER, does not include JESD204C interface BER 10–18 Errors/ sample
NOISEDC DC input noise standard deviation No input, foreground calibration, excludes DC offset, includes fixed interleaving spur (fS / 2 spur) 2.3 LSB
NSD Noise spectral density, excludes fixed interleaving spur (fS / 2 spur) Maximum full-scale voltage (VFS = 1.0 VPP), AIN = –20 dBFS –152.0 dBFS/
Hz
Default full-scale voltage (VFS = 0.8 VPP), AIN = –20 dBFS –150.4
NF Noise figure, ZS = 100 Ω Maximum full-scale voltage (VFS = 1.0 VPP), AIN = –20 dBFS 23.0 dB
Default full-scale voltage (VFS = 0.8 VPP), AIN = –20 dBFS 22.6
SNR Signal-to-noise ratio, excluding DC, HD2 to HD9, fS / 2, fS / 2 – fIN, fIN = 347 MHz AIN = –1 dBFS 55.6 dBFS
AIN = –3 dBFS 55.9
AIN = –12 dBFS 56.3
AIN = –3 dBFS, VFS = 1.0 VPP 57.2
fIN = 997 MHz AIN = –1 dBFS 55.4
AIN = –3 dBFS 55.8
AIN = –12 dBFS 56.3
fIN = 2397 MHz AIN = –1 dBFS, TA = -55℃ 48
AIN = –1 dBFS, TA = 25℃ 52 54.7
AIN = –1 dBFS, TA = 125℃ 51
AIN = –3 dBFS 55.2
AIN = –12 dBFS 56.2
AIN = –3 dBFS, VFS = 1.0 VPP 56.3
fIN = 4197 MHz AIN = –1 dBFS 53.0
AIN = –3 dBFS 54.0
AIN = –12 dBFS 56.0
fIN = 5997 MHz AIN = –1 dBFS 51.4
AIN = –3 dBFS 52.6
AIN = –12 dBFS 55.6
fIN = 7997 MHz AIN = –1 dBFS 49.6
AIN = –3 dBFS 51.1
AIN = –12 dBFS 55.2
SINAD Signal-to-noise and distortion ratio, excluding DC and fS / 2 fixed spurs fIN = 347 MHz AIN = –1 dBFS 54.5 dBFS
AIN = –3 dBFS 55.3
AIN = –12 dBFS 56.1
AIN = –3 dBFS, VFS = 1.0 VPP 56.3
fIN = 997 MHz AIN = –1 dBFS 54.4
AIN = –3 dBFS 55.3
AIN = –12 dBFS 56.1
fIN = 2397 MHz AIN = –1 dBFS, TA = -55℃ 46
AIN = –1 dBFS, TA = 25℃ 49 53.9
AIN = –1 dBFS, TA = 125℃ 48
AIN = –3 dBFS 54.7
AIN = –12 dBFS 56.1
AIN = –3 dBFS, VFS = 1.0 VPP 55.7
fIN = 4197 MHz AIN = –1 dBFS 51.5
AIN = –3 dBFS 53.2
AIN = –12 dBFS 55.8
fIN = 5997 MHz AIN = –1 dBFS 48.8
AIN = –3 dBFS 51.5
AIN = –12 dBFS 55.5
fIN = 7997 MHz AIN = –1 dBFS 46.2
AIN = –3 dBFS 49.2
AIN = –12 dBFS 55.0
ENOB Effective number of bits, excluding DC and fS / 2 fixed spurs fIN = 347 MHz AIN = –1 dBFS 8.8 bits
AIN = –3 dBFS 8.9
AIN = –12 dBFS 9.0
AIN = –3 dBFS, VFS = 1.0 VPP 9.1
fIN = 997 MHz AIN = –1 dBFS 8.7
AIN = –3 dBFS 8.9
AIN = -12 dBFS 9.0
fIN = 2397 MHz AIN = –1 dBFS, TA = -55℃ 7.35
AIN = –1 dBFS, TA = 25℃ 7.85 8.7
AIN = –1 dBFS, TA = 125℃ 7.7
AIN = –3 dBFS 8.8
AIN = –12 dBFS 9.0
AIN = –3 dBFS, VFS = 1.0 VPP 9.0
fIN = 4197 MHz AIN = –1 dBFS 8.3
AIN = –3 dBFS 8.5
AIN = –12 dBFS 9.0
fIN = 5997 MHz AIN = –1 dBFS 7.8
AIN = –3 dBFS 8.3
AIN = –12 dBFS 8.9
fIN = 7997 MHz AIN = –1 dBFS 7.4
AIN = –3 dBFS 7.9
AIN = –12 dBFS 8.8
SFDR Spurious-free dynamic range, excluding DC and fS / 2 fixed spurs fIN = 347 MHz AIN = –1 dBFS 65 dBFS
AIN = –3 dBFS 67
AIN = –12 dBFS 73
AIN = –3 dBFS, VFS = 1.0 VPP 67
fIN = 997 MHz AIN = –1 dBFS 64
AIN = –3 dBFS 69
AIN = –12 dBFS 74
fIN = 2397 MHz AIN = –1 dBFS 52 65
AIN = –3 dBFS 67
AIN = –12 dBFS 73
AIN = –3 dBFS, VFS = 1.0 VPP 68
fIN = 4197 MHz AIN = –1 dBFS 59
AIN = –3 dBFS 64
AIN = –12 dBFS 73
fIN = 5997 MHz AIN = –1 dBFS 54
AIN = –3 dBFS 61
AIN = –12 dBFS 75
fIN = 7997 MHz AIN = –1 dBFS 50
AIN = –3 dBFS 56
AIN = –12 dBFS 71
HD2 2nd-order harmonic distortion fIN = 347 MHz AIN = –1 dBFS –74 dBFS
AIN = –3 dBFS –76
AIN = –12 dBFS –84
AIN = –3 dBFS, VFS = 1.0 VPP –76
fIN = 997 MHz AIN = –1 dBFS –78
AIN = –3 dBFS –77
AIN = –12 dBFS –81
fIN = 2397 MHz AIN = –1 dBFS –72 -58
AIN = –3 dBFS –72
AIN = –12 dBFS –82
AIN = –3 dBFS, VFS = 1.0 VPP –73
fIN = 4197 MHz AIN = –1 dBFS –64
AIN = –3 dBFS –69
AIN = –12 dBFS –83
fIN = 5997 MHz AIN = –1 dBFS –65
AIN = –3 dBFS –67
AIN = –12 dBFS –79
fIN = 7997 MHz AIN = –1 dBFS –59
AIN = –3 dBFS –63
AIN = –12 dBFS –81
HD3 3rd-order harmonic distortion fIN = 347 MHz AIN = –1 dBFS –65 dBFS
AIN = –3 dBFS –72
AIN = –12 dBFS –81
AIN = –3 dBFS, VFS = 1.0 VPP –65
fIN = 997 MHz AIN = –1 dBFS –65
AIN = –3 dBFS –76
AIN = –12 dBFS –81
fIN = 2397 MHz AIN = –1 dBFS –67 -58
AIN = –3 dBFS –74
AIN = –12 dBFS –84
AIN = –3 dBFS, VFS = 1.0 VPP –71
fIN = 4197 MHz AIN = –1 dBFS –65
AIN = –3 dBFS –66
AIN = –12 dBFS –79
fIN = 5997 MHz AIN = –1 dBFS –55
AIN = –3 dBFS –62
AIN = –12 dBFS –82
fIN = 7997 MHz AIN = –1 dBFS –50
AIN = –3 dBFS –56
AIN = –12 dBFS –80
fS / 2 – fIN fS / 2 – fIN input signal dependent interleaving spur fIN = 347 MHz AIN = –1 dBFS –69 dBFS
AIN = –3 dBFS –70
AIN = –12 dBFS –76
AIN = –3 dBFS, VFS = 1.0 VPP –71
fIN = 997 MHz AIN = –1 dBFS –67
AIN = –3 dBFS –70
AIN = –12 dBFS –77
fIN = 2397 MHz AIN = –1 dBFS –68 -52
AIN = –3 dBFS –68
AIN = –12 dBFS –74
AIN = –3 dBFS, VFS = 1.0 VPP –70
fIN = 4197 MHz AIN = –1 dBFS –67
AIN = –3 dBFS –68
AIN = –12 dBFS –74
fIN = 5997 MHz AIN = –1 dBFS –68
AIN = –3 dBFS –68
AIN = –12 dBFS –77
fIN = 7997 MHz AIN = –1 dBFS –61
AIN = –3 dBFS –63
AIN = –12 dBFS –71
fS / 2 fS / 2 fixed interleaving spur, independent of input signal AIN = –20 dBFS –73 -55 dBFS
SPUR Worst spur, excluding DC, HD2, HD3, fS / 2 and fS / 2 - fIN spurs fIN = 347 MHz AIN = –1 dBFS –74 dBFS
AIN = –3 dBFS –75
AIN = –12 dBFS –80
AIN = –3 dBFS, VFS = 1.0 VPP –76
fIN = 997 MHz AIN = –1 dBFS –73
AIN = –3 dBFS –74
AIN = –12 dBFS –79
fIN = 2397 MHz AIN = –1 dBFS –74 -62
AIN = –3 dBFS –75
AIN = –12 dBFS –80
AIN = –3 dBFS, VFS = 1.0 VPP –76
fIN = 4197 MHz AIN = –1 dBFS –71
AIN = –3 dBFS –74
AIN = –12 dBFS –78
fIN = 5997 MHz AIN = –1 dBFS –68
AIN = –3 dBFS –72
AIN = –12 dBFS –79
fIN = 7997 MHz AIN = –1 dBFS –71
AIN = –3 dBFS –73
AIN = –12 dBFS –78
IMD3 3rd-order intermodulation distortion f1 = 343 MHz,
f2 = 353 MHz		 AIN = –7 dBFS per tone –78 dBFS
AIN = –9 dBFS per tone –82
AIN = –18 dBFS per tone –90
AIN = –9 dBFS per tone, VFS = 1.0 VPP –85
f1 = 993 MHz,
f2 = 1003 MHz		 AIN = –7 dBFS per tone –82
AIN = –9 dBFS per tone –85
AIN = –18 dBFS per tone –86
f1 = 2393 MHz,
f2 = 2403 MHz		 AIN = –7 dBFS per tone –78
AIN = –9 dBFS per tone –83
AIN = –18 dBFS per tone –92
AIN = –9 dBFS per tone, VFS = 1.0 VPP –81
f1 = 4193 MHz,
f2 = 4203 MHz		 AIN = –7 dBFS per tone –70
AIN = –9 dBFS per tone –75
AIN = –18 dBFS per tone –85
f1 = 5993 MHz,
f2 = 6003 MHz		 AIN = –7 dBFS per tone –56
AIN = –9 dBFS per tone –63
AIN = –18 dBFS per tone –91
f1 = 7993 MHz,
f2 = 8003 MHz		 AIN = –7 dBFS per tone –48
AIN = –9 dBFS per tone –54
AIN = –18 dBFS per tone –83
(1) Full-power input bandwidth (FPBW) is defined as the input frequency where the reconstructed output of the ADC has dropped 3 dB below the power of a full-scale input signal at a low input frequency. Useable bandwidth may exceed the –3-dB, full-power input bandwidth.
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