ZHCSOJ3B March 2023 – June 2024 ADC12DJ5200SE
PRODUCTION DATA
The PD input pin allows the devices to be entirely powered down. Power-down can also be controlled by MODE (see the device configuration register). To power down only one channel in dual channel mode use the channel power down register. The serial data output drivers are disabled when PD is high. For proper operation in foreground calibration mode, ADC_OFF in the CAL_CFG register should be programmed to 0x1. When the device returns to normal operation, the JESD204 link must be re-established, and the ADC pipeline and decimation filters contain meaningless information so the system must wait a sufficient time for the data to be flushed.