ZHCSOJ3B March 2023 – June 2024 ADC12DJ5200SE
PRODUCTION DATA
Within each channel DDC, four different frequency and phase settings are available for use. Each of the four settings use a different phase accumulator within the NCO. Because all four phase accumulators are independent and continuously running, rapid switching between different NCO frequencies is possible allowing for phase coherent frequency hopping.
The specific frequency-phase pair used for each channel is selected through the NCOA[1:0] or NCOB[1:0] input pins when CMODE is set to 1. Alternatively, the selected NCO can be chosen through SPI by CSELA for DDC A and CSELB for DDC B by setting CMODE to 0 (default). The logic table for NCO selection is provided in Table 6-11 for both the GPIO and SPI selection options.
| NCO SELECTION | CMODE | NCOx1 | NCOx0 | CSELx[1] | CSELx[0] |
|---|---|---|---|---|---|
| NCO 0 using GPIO | 1 | 0 | 0 | X | X |
| NCO 1 using GPIO | 1 | 0 | 1 | X | X |
| NCO 2 using GPIO | 1 | 1 | 0 | X | X |
| NCO 3 using GPIO | 1 | 1 | 1 | X | X |
| NCO 0 using SPI | 0 | X | X | 0 | 0 |
| NCO 1 using SPI | 0 | X | X | 0 | 1 |
| NCO 2 using SPI | 0 | X | X | 1 | 0 |
| NCO 3 using SPI | 0 | X | X | 1 | 1 |
The frequency for each phase accumulator is programmed independently through the FREQAx, FREQBx (x = 0 to 3) and, optionally, NCO_RDIV register settings. The phase offset for each accumulator is programmed independently through the PHASEAx and PHASEBx (x = 0 to 3) register settings.