ZHCSOJ3B March 2023 – June 2024 ADC12DJ5200SE
PRODUCTION DATA
Table 6-66 lists the parameters that can be trimmed and the associated registers. User trimming is limited to foreground (FG) calibration mode only.
| TRIM PARAMETER | TRIM REGISTER | NOTES |
|---|---|---|
| Band-gap reference | BG_TRIM | Measurement on BG output pin. |
| Input termination resistance | RTRIM_x, where x = A for INA or B for INB) | The device must be powered on with a clock applied. |
| Input offset voltage | OADJ_A_FG0_VINx, OADJ_A_FG90_VINx and OADJ_B_FG0_VINx, where OADJ_A applies to ADC core A and OADJ_B applies to ADC core B, FG0 applies to dual channel mode for ADC cores A and B and single channel mode for ADC core B, FG90 applies to ADC core A in single channel mode and x = A for INA or B for INB) | Input offset adjustment in dual channel mode consists of changing OADJ_A_FG0_VINA for channel A and OADJ_B_FG0_VINB for channel B. In single channel mode, OADJ_A_FG90_VINx and OADJ_B_FG0_VINx must be adjusted together to trim the input offset or adjusted separate to compensate the fS/2 offset spur. |
| INA and INB gain | GAIN_xy_FGDUAL or GAIN_xy_FGDES, where x = ADC channel (A or B) and y = bank number (0 or 1) | Set FS_RANGE_A and FS_RANGE_B to default values before trimming the input. Use FS_RANGE_A and FS_RANGE_B to adjust the full-scale input voltage. The GAIN_xy_FGDUAL registers apply to Dual Channel Mode and the GAIN_xy_FGDES registers apply to the Single Channel Mode. To trim the gain of ADC core A or B, change GAIN_x0_FGDUAL and GAIN_x1_FGDUAL (or GAIN_x0_FGDES and GAIN_x1_FGDES) together in the same direction. To trim the gain of the two banks within ADC A or B, change GAIN_x0_FGDUAL and GAIN_x1_FGDUAL (or GAIN_x0_FGDES and GAIN_x1_FGDES) in opposite directions. |
| INA and INB full-scale input voltage | FS_RANGE_x, where x = A for INA or B for INB) | Full-scale input voltage adjustment for each input. The default value is effected by GAIN_Bx (x = 0, 1, 4 or 5). Trim GAIN_Bx with FS_RANGE_x set to the default value. FS_RANGE_x can then be used to trim the full-scale input voltage. |
| Intra-ADC core timing (bank timing) | Bx_TIME_y, where x = bank number (0, 1, 4 or 5) and y = 0° (0) or –90° (90) clock phase | Trims the timing between the two banks of an ADC core (ADC A or B). The 0° clock phase is used for dual channel mode and for ADC B in single channel mode. The –90° clock phase is used only for ADC A in single-channel mode. A mismatch in the timing between the two banks of an ADC core can result in an fS/2-fIN spur in dual channel mode or fS/4±fIN spurs in single channel mode. |
| Inter-ADC core timing (dual-channel mode) | TADJ_A, TADJ_B | The suffix letter (A or B) indicates the ADC core that is being trimmed. Changing either TADJ_A or TADJ_B adjusts the sampling instance of ADC A relative to ADC B in dual channel mode. |
| Inter-ADC core timing (single-channel mode) | TADJ_A_FG90_VINx, TADJ_B_FG0_VINx, where x = analog input (INA or INB) | These trim registers are used to adjust the timing of ADC core A relative to ADC core B in single channel mode. A mismatch in the timing will result in an fS/2-fIN spur that is signal dependent. Changing either TADJ_A_FG90_VINx or TADJ_B_FG0_VINx changes the relative timing of ADC core A relative to ADC core B in single channel mode. |