ZHCSON7A July 2021 – October 2024 ADC12DJ800-Q1 , ADC12QJ800-Q1 , ADC12SJ800-Q1
PRODUCTION DATA
The example LiDAR system uses four ADC channels running at 800MSPS and the on-chip clock features of the device to reduce the system size and cost. The device is clocked by a 50-MHz crystal through the single-ended clock input (CLK_SE) and the integrated clock features are used to eliminate external clocking components. The internal PLL (C-PLL) generates the 800 MHz sampling clock for the ADC cores. The 50 MHz PLL reference is repeated through the PLLREFO output to the FPGA to generate the FPGA internal clocks including the application layer clock. The 50 MHz reference is divided down in the FPGA to generate the SYSREF signal which is sent to both the FPGA JESD204C core and to the device to achieve deterministic latency.
There are a number of clocking frequencies used in the example system shown in Figure 7-1. The reference clock frequency (fREF) is chosen by the designer and in this case is chosen as 50 MHz, which is the minimum supported reference frequency and which multiplies easily to 800 MHz. The sampling rate is set by the system requirements which is 800 MSPS (fS). The V, P and N dividers of the C-PLL are chosen as described in the Coverter PLL (C-PLL) section which, along with the reference frequency, determines the VCO frequency (fVCO). JMODE 8 was chosen to stay within the FPGA SerDes requirements (4 lanes, 12.5 Gbps max rate) which is a 64B/66B mode. TRIGOUT provides the FPGA SerDes PLL reference clock to the FPGA (fTRIGOUT) and PLLREFO provides the reference clock for the FPGA core logic. ORC (fORC) and ORD (fORD) provide additional clock outputs, if needed, for the FPGA or peripheral devices. SYSREF is generated within the FPGA and sent to the ADC in order to achieve deterministic latency. This is not usually recommended due to timing constraints, however the low reference frequency (50 MHz) significantly relaxes the SYSREF setup and hold timing and the SYSREF Windowing feature allows verification of proper capture timing of SYSREF relative to the reference clock. The SYSREF frequency must divide evenly into the reference clock frequency, in addition to meeting the JESD204 protocol requirements, in order to achieve deterministic latency due to the use of the C-PLL. The frequency and rate calculations are summarized in Table 7-2.
| Clock | Symbol | Calculation | Frequency |
|---|---|---|---|
| Reference Clock | fREF | Chosen by designer | 50 MHz |
| Sampling Rate | fS | System requirement | 800 MSPS |
| C-PLL VCO | fVCO | fVCO = fSx P x V where P is 2 and V is 5 | 8 GHz |
| SerDes Linerate | fLINERATE | fLINERATE = fSx R where R is 12.375 for JMODE 8 (see Table 6-16, Table 6-17 and Table 6-18) | 9.9 Gbps / Lane (4 lanes) |
| TRIGOUT Clock Output | fTRIGOUT | fTRIGOUT = fLINERATE/ RX_DIV where RX_DIV is 32 (TRIGOUT_CTRL=0x81) | 309.375 MHz |
| SYSREF | fSYSREF | fSYSREF = fLINERATE/(66 x 32 x E x n) where E is 3 for JMODE 8 (64B or 66B mode) and n is chosen such that fSYSREF is an integer division of fREF (n = 5) | 312.5 kHz |
| ORC Clock Output | fORC | fORC = fREF/2 (See Table 6-5) | 25 MHz |
| ORD Clock Output | fORD | fORD = fREF (See Table 6-6) | 50 MHz |
| FPGA Core Clock | fFPGA | fFPGA = fREF x M(1)(2) where M is an integer value, chosen as 5 | 250 MHz (4 samples per cycle) |