ZHCSON7A July   2021  – October 2024 ADC12DJ800-Q1 , ADC12QJ800-Q1 , ADC12SJ800-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: DC Specifications
    6. 5.6  Electrical Characteristics: Power Consumption
    7. 5.7  Electrical Characteristics: AC Specifications
    8. 5.8  Timing Requirements
    9. 5.9  Switching Characteristics
    10. 5.10 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Device Comparison
      2. 6.3.2 Analog Input
        1. 6.3.2.1 Analog Input Protection
        2. 6.3.2.2 Full-Scale Voltage (VFS) Adjustment
        3. 6.3.2.3 Analog Input Offset Adjust
        4. 6.3.2.4 ADC Core
          1. 6.3.2.4.1 ADC Theory of Operation
          2. 6.3.2.4.2 ADC Core Calibration
          3. 6.3.2.4.3 Analog Reference Voltage
          4. 6.3.2.4.4 ADC Over-range Detection
          5. 6.3.2.4.5 Code Error Rate (CER)
      3. 6.3.3 Temperature Monitoring Diode
      4. 6.3.4 Timestamp
      5. 6.3.5 Clocking
        1. 6.3.5.1 Converter PLL (C-PLL) for Sampling Clock Generation
        2. 6.3.5.2 LVDS Clock Outputs (PLLREFO±, TRIGOUT±)
        3. 6.3.5.3 Optional CMOS Clock Outputs (ORC, ORD)
        4. 6.3.5.4 SYSREF for JESD204C Subclass-1 Deterministic Latency
          1. 6.3.5.4.1 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          2. 6.3.5.4.2 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
      6. 6.3.6 JESD204C Interface
        1. 6.3.6.1  Transport Layer
        2. 6.3.6.2  Scrambler
        3. 6.3.6.3  Link Layer
        4. 6.3.6.4  8B/10B Link Layer
          1. 6.3.6.4.1 Data Encoding (8B/10B)
          2. 6.3.6.4.2 Multiframes and the Local Multiframe Clock (LMFC)
          3. 6.3.6.4.3 Code Group Synchronization (CGS)
          4. 6.3.6.4.4 Initial Lane Alignment Sequence (ILAS)
          5. 6.3.6.4.5 Frame and Multiframe Monitoring
        5. 6.3.6.5  64B/66B Link Layer
          1. 6.3.6.5.1 64B/66B Encoding
          2. 6.3.6.5.2 Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)
            1. 6.3.6.5.2.1 Block, Multiblock and Extended Multiblock Alignment using Sync Header
              1. 6.3.6.5.2.1.1 Cyclic Redundancy Check (CRC) Mode
              2. 6.3.6.5.2.1.2 Forward Error Correction (FEC) Mode
          3. 6.3.6.5.3 Initial Lane Alignment
          4. 6.3.6.5.4 Block, Multiblock and Extended Multiblock Alignment Monitoring
        6. 6.3.6.6  Physical Layer
          1. 6.3.6.6.1 SerDes Pre-Emphasis
        7. 6.3.6.7  JESD204C Enable
        8. 6.3.6.8  Multi-Device Synchronization and Deterministic Latency
        9. 6.3.6.9  Operation in Subclass 0 Systems
        10. 6.3.6.10 Alarm Monitoring
          1. 6.3.6.10.1 Clock Upset Detection
          2. 6.3.6.10.2 FIFO Upset Detection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Low Power Mode and High Performance Mode
      2. 6.4.2 JESD204C Modes
        1. 6.4.2.1 JESD204C Transport Layer Data Formats
        2. 6.4.2.2 64B/66B Sync Header Stream Configuration
        3. 6.4.2.3 Redundant Data Mode (Alternate Lanes)
      3. 6.4.3 Power-Down Modes
      4. 6.4.4 Test Modes
        1. 6.4.4.1 Serializer Test-Mode Details
        2. 6.4.4.2 PRBS Test Modes
        3. 6.4.4.3 Clock Pattern Mode
        4. 6.4.4.4 Ramp Test Mode
        5. 6.4.4.5 Short and Long Transport Test Mode
          1. 6.4.4.5.1 Short Transport Test Pattern
        6. 6.4.4.6 D21.5 Test Mode
        7. 6.4.4.7 K28.5 Test Mode
        8. 6.4.4.8 Repeated ILA Test Mode
        9. 6.4.4.9 Modified RPAT Test Mode
      5. 6.4.5 Calibration Modes and Trimming
        1. 6.4.5.1 Foreground Calibration Mode
        2. 6.4.5.2 Background Calibration Mode
        3. 6.4.5.3 Low-Power Background Calibration (LPBG) Mode
      6. 6.4.6 Offset Calibration
      7. 6.4.7 Trimming
    5. 6.5 Programming
      1. 6.5.1 Using the Serial Interface
      2. 6.5.2 SCS
      3. 6.5.3 SCLK
      4. 6.5.4 SDI
      5. 6.5.5 SDO
      6. 6.5.6 Streaming Mode
      7. 6.5.7 SPI_Register_Map Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Light Detection and Ranging (LiDAR) Digitizer
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Analog Front-End Requirements
          2. 7.2.1.2.2 Calculating Clock and SerDes Frequencies
        3. 7.2.1.3 Application Curves
    3. 7.3 Initialization Set Up
    4. 7.4 Power Supply Recommendations
      1. 7.4.1 Power Sequencing
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
    2. 8.2 接收文档更新通知
    3. 8.3 支持资源
    4. 8.4 商标
    5. 8.5 静电放电警告
    6. 8.6 术语表
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

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6.3.6 JESD204C Interface

The device uses a JESD204C high-speed serial interface for data converters to transfer data from the ADC to the receiving logic device. The device serialized lanes are capable of operating with both 8B/10B encoding and 64B/66B encoding. The JESD204C output formats using 8B/10B encoding are backwards compatible with existing JESD204B receivers. A maximum of 8 lanes can be used to lower lane rates for interfacing with speed-limited logic devices. There are a few differences between 8B/10B and 64B/66B encoded JESD204C, which is highlighted throughout this section. Figure 6-7 shows a simplified block diagram of the 8B/10B encoded JESD204C interface and Figure 6-8 shows a simplified block diagram of the 64B/66B encoded JESD204C interface.

ADC12QJ800-Q1 ADC12DJ800-Q1 ADC12SJ800-Q1 Simplified 8B/10B Encoded JESD204C Interface DiagramFigure 6-7 Simplified 8B/10B Encoded JESD204C Interface Diagram
ADC12QJ800-Q1 ADC12DJ800-Q1 ADC12SJ800-Q1 Simplified 64B/66B Encoded JESD204C Interface Diagram Figure 6-8 Simplified 64B/66B Encoded JESD204C Interface Diagram

The various signals used in the JESD204C interface and the associated ADC12xJ800-Q1 pin names are summarized briefly in Table 6-8 for reference. Most of the signals are common between 8B/10B and 64B/66B encoded JESD204C, except for SYNC which is not needed to achieve block synchronization for 64B/66B encoding. The sync header encoded into the data stream is used for block synchronization instead of the SYNC signal.

Table 6-8 Summary of JESD204C Signals
SIGNAL NAMEPIN NAMES8B/10B64B/66BDESCRIPTION
DataQuad/dual channel: D[7:0]+, D[7:0]–
Single channel: D[3:0]+, D[3:0]–		YesYesHigh-speed serialized data after 8B/10B or 64B/66B encoding
SYNCSYNCSEYesNoLink initialization signal (handshake), toggles low to start code group synchronization (CGS) process. Not used for 64B/66B encoding modes, unless it is used for NCO synchronization purposes.
Device clockCLK+, CLK– or SE_CLKYesYesADC sampling clock or PLL reference clock, also used for clocking digital logic and output serializers
SYSREFSYSREF+, SYSREF–YesYesSystem timing reference used to deterministically reset the internal local multiframe clock (LMFC) or local extended multiblock clock (LEMC) counters in each JESD204C device

Not all optional features of JESD204C are supported by ADC12xJ800-Q1. The list of features that are supported and the features that are not supported is provided in Table 6-9.

Table 6-9 Declaration of Supported JESD204C Features
LETTER IDENTIFIERREFERENCE CLAUSEFEATURESUPPORT IN ADC12xJ800-Q1
aclause 88B/10B link layerSupported
bclause 764B/66B link layerSupported
cclause 764B/80B link layerNot supported
dclause 7The command channel when using the 64B/66B or 64B/80B link layerNot supported
eclause 7Forward error correction (FEC) when using the 64B/66B or 64B/80B link layerSupported
fclause 7CRC3 when using the 64B/66B or 64B/80B link layerNot supported
gclause 8A physical SYNC pin when using the 8B/10B link layerSupported
hclause 7, clause 8Subclass 0Not supported, but subclass 1 transmitter is compatible with subclass 0 receiver
iclause 7, clause 8Subclass 1Supported
jclause 8Subclass 2Not supported
kclause 7, clause 8Lane alignment within a single linkSupported
lclause 7, clause 8Subclass 1 with support for a lane alignment on a multipoint link by means of the MULTIREF signalNot supported
mclause 8SYNC interface timing is compatible with JESD204ASupported
nclause 8SYNC interface timing is compatible with JESD204BSupported
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