Setting this bit causes a full reset of the device and all SPI registers (including CONFIG_A). This bit is self-clearing. After writing this bit, the device may take up to 750 ns to reset. During this time, do not perform any SPI transactions.

Reserved

0 : Address is decremented during streaming reads or writes
1 : Address is incremented during streaming reads or writes (default)

Always returns 1. Always use SDO for SPI reads.
No SDIO mode is supported.

Reserved

Reserved

Always returns 0x3, indicating that the device is a high-speed ADC.

Reserved

0 : Use the ASCEND register to select address ascend or descend mode (default)
1 : Address stays constant throughout streaming operation; useful for reading and writing calibration vector information at the CAL_DATA register

Reserved

The SYSREF signal is output on the LSB of the LVDS output samples when SYSREF_TIMESTAMP_EN and TIME_STAMP_EN are both set. This bit allows SYSREF± to be used as the timestamp input.

Activate DC-coupled, low-voltage PECL mode for CLK±; see the Pin Functions table.

Activate DC-coupled, low-voltage PECL mode for SYSREF±; see the Pin Functions table.

This bit inverts the SYSREF signal used for alignment.

Reserved

When set, VA11 is used as the voltage reference instead of the band-gap voltage.

Reserved

These bits set the swing mode of the LVDS output buffers:
0 : High-swing mode (HSM) (default)
1 : Low-swing mode (LSM)
2 : Reserved (do not use)
3 : Low-swing mode for use with receivers that have a high-Z load termination (HZM). Only use with short transmission lines to avoid reflections caused by a high-Z receiver.

Reserved

This bit enables calibration. Set this bit high to run calibration. Set this bit low to hold calibration in reset to program new calibration settings. Clearing CAL_EN also resets the clock dividers that clock the encoders and LVDS interface.

Note 1: Many calibration SPI registers are not synchronized to the internal clock that runs the calibration logic. Changing these registers may corrupt the calibration state machine. Always clear CAL_EN before making any changes to these registers. All registers with this requirement contain a note in their descriptions. After changing the registers, set CAL_EN to re-run calibration with the new settings.

Note 2: Always set CAL_EN before setting LVDS_EN.

Note 3: Always clear LVDS_EN before clearing CAL_EN.

Reserved

Select the amount of averaging used for each measurement of the offset correction search. A larger number corresponds to more averaging.

Reserved

0 : CALSTAT output pin matches FG_DONE
1 : CALSTAT output pin matches CAL_STOPPED
2 : CALSTAT output pin matches ALARM
3 : CALSTAT output is always low

This bit selects the hardware or software trigger source.
0 : Use the CAL_SOFT_TRIG register for the calibration trigger. The CALTRIG input is disabled (ignored).
1 : Use the CALTRIG input for the calibration trigger. The CAL_SOFT_TRIG register is ignored.

Reserved

This register enables gain trim of channel A. After reset, the factory trimmed value can be read and adjusted as required. Use FS_RANGE_A to adjust the analog full-scale voltage (V_fs) of INA±.

Reserved

This register enables trimming of the internal band-gap reference. After reset, the factory trimmed value can be read and adjusted as required.

Time adjustment for bank 0 applied when ADC is configured for –90° clock phase (single channel mode).

Time adjustment for bank 1 applied when ADC is configured for –90° clock phase (single channel mode).

Reserved

Reserved

Defines the value for sample 1 of the user defined pattern. See UPAT0 register.
Note: Only change this register when LVDS_EN = 0.

Defines the value for sample 3 of the user defined pattern. See UPAT0 register.
Note: Only change this register when LVDS_EN = 0.

Reserved

Defines the value for sample 5 of the user defined pattern. See UPAT0 register.
Note: Only change this register when LVDS_EN = 0.

Reserved

Defines the value for sample 7 of the user defined pattern. See UPAT0 register.
Note: Only change this register when LVDS_EN = 0.

Reserved

Reserved

Specifies the sample width for the LVDS output interface.
0 : 12-bit sample width (default)
1 : 11-bit sample width
2 : 10-bit sample width
3 : 8-bit sample width

Reserved

0 : Disable DES mode (enable dual channel mode)
1 : Enable DES mode (enable single channel mode)
CAL_EN must be 0 before changing DES_EN.

0 : The LVDS buses are staggered for optimized switching noise and latency.
1 : The LVDS buses are aligned for simplified timing.

0 : Demux-by-1, uses 2 LVDS buses total
1 : Demux-by-2, uses 4 LVDS buses total

Defines the number of UIs in each LVDS frame. Any multiple of 4 from 4 to 128 is supported. All other values are unsupported.

When LDEMUX=0, one UI is one CLK± cycle.
When LDEMUX=1, one UI is two CLK± cycles.

Note: Setting LFRAME to 4 is not recommended, as it may be difficult to achieve deterministic latency over all process, voltage, and temperature conditions. The propagation delay variation may be larger than the frame period.

Reserved

Set this bit to 0 to request LVDS synchronization (equivalent to the hardware SYNC signal being asserted, as selected by SYNC_SEL). For normal operation, leave this bit set to 1.

Note: The LSYNC_N register can always generate a synchronization request, regardless of the SYNC_SEL setting in the LCTRL register. However, if the selected sync pin is stuck low, the synchronization request cannot be de-asserted unless SYNC_SEL=2.

Enable DDSTB± output

Enable DCSTB± output

Enable DBSTB± output

Enable DASTB± output

Enable DDCLK± output

Enable DCCLK± output

Enable DBCLK± output

Enable DACLK± output

Returns the instantaneous state of the LVDS interface SYNC signal ( SYNC_SE or TMSTP±).
0 : SYNC asserted
1 : SYNC de-asserted

When high, indicates that SYSREF realigned internal clocks. REALIGNED_ALM should be used for monitoring of realignment events instead of this bit. Writing a 1 to this bit will clear it, but will not affect the REALIGNED_ALM bit.

When high, indicates that internal clock phases have been established by SYSREF. Any SYSREF rising edge that is processed after enabling the LVDS system will set this bit. This bit can be monitored during startup to verify that SYSREF has been processed before continuing system initialization. Writing a 1 to this bit will clear it and the next SYSREF event will set it again.

This parameter defines the absolute sample level that causes OVA0 or OVB0 to be set. The detection level in dBFS (peak) is 20log10(OVR_T0/256) (default: 0xF2 = 242 –> -0.5dBFS)

Reserved

ORA0, ORA1, ORB0 and ORB1 outputs pins are enabled and output the overrange status when this bit is set high. The outputs are held low when this bit is set low.

Program this register to adjust the pulse length for the ORA0, ORA1 and ORB0, ORB1 outputs.
The minimum pulse duration of the overrange outputs is 8 × 2^OVR_N CLK± cycles.

Reserved

Reserved

This bit returns ‘1’ when SRC_EN=1 and SYSREF Calibration has been completed.

Reserved

Reserved

This bit returns a ‘1’ whenever any unmasked alarm is set in the ALM_STATUS register. Use ALM_MASK to mask (disable) individual alarms.
CAL_STATUS_SEL can be used to drive the ALARM bit onto the CAL_STAT pin to provide a hardware alarm interrupt signal.

Reserved

When set, REALIGNED_ALM is masked and will not impact the ALARM register bit.

Reserved

When set, CLK_ALM is masked and will not impact the ALARM register bit.

Reserved

Offset adjustment value applied to A-ADC when it samples INB± using 0° clock phase and foreground calibration is enabled.

Reserved

Offset adjustment value applied to A-ADC when it samples INB± using 90° clock phase and foreground calibration is enabled.

Reserved

Offset adjustment value applied to B-ADC when it samples INB± using 0° clock phase and foreground calibration is enabled.

Reserved

Fine gain adjustment for bank 1.

Reserved

Fine gain adjustment for bank 5.