ZHCSI83C may 2018 – may 2023 ADC12DL3200
PRODUCTION DATA
Table 7-17 lists the parameters that can be trimmed and the associated registers. Manual trimming is only allowed in foreground calibration mode.
| TRIM PARAMETER | TRIM REGISTER | NOTES |
|---|---|---|
| Band-gap reference | BG_TRIM | Measurement on the BG output pin. |
| Input termination resistance | RTRIM_x, where x = A for INA± or B for INB±) | The device must be powered on with a clock applied. |
| Input offset voltage | OADJ_x_FG0_VINy and OADJ_A_FG90_VINy, where x = ADC core (A or B) and y = A for INA± or B for INB± | A different trim value is allowed for each ADC core (A or B) to allow trimming of the offsets as operating conditions change. OADJ_A_FG90_VINy is used to trim the offsets of ADC A in single-channel mode. |
| INA± and INB± gain | GAIN_TRIM_x, where x = A for INA± or B for INB± | Set FS_RANGE_A and FS_RANGE_B to default values before trimming the input. Use FS_RANGE_A and FS_RANGE_B to adjust the full-scale input voltage. |
| Bank gain trim | GAIN_Bx, where x = 0, 1, 2, or 3 | Trims the gain of the individual ADC banks to improve gain matching between ADC cores. |
| INA± and INB± full-scale input voltage | FS_RANGE_x, where x = A for INA± or B for INB± | Full-scale input voltage adjustment for each input. The default value is effected by GAIN_TRIM_x (x = A or B). Trim GAIN_TRIM_x with FS_RANGE_x set to the default value. FS_RANGE_x can then be used to trim the full-scale input voltage. |
| Intra-ADC core timing (bank timing) | Bx_TIME_y, where x = bank number (0–5) and y = 0° or –90° clock phase | Trims the timing between the two banks of an ADC core (ADC A or B) for two clock phases, either 0° or –90°. The –90° clock phase is used by ADC A in single-channel mode only. |
| Inter-ADC core timing (dual-channel mode) | TADJ_A, TADJ_B | The suffix letter (A or B) indicates the ADC core that is being trimmed. |
| Inter-ADC core timing (single-channel mode) | TADJ_A_FG90, TADJ_B_FG0 | The middle letter (A or B) indicates the ADC core that is being trimmed. The suffix of 0 or 90 indicates the clock phase applied to the ADC core. 0 indicates a 0° clock and is sampling in-phase with the clock input (applies to ADC B). 90 indicates a –90° clock and therefore is sampling out-of-phase with the clock input (applies to ADC A). |