In four LVDS output modes (see Table 7-11), the data clock (DxCLK±) and strobe (DxSTR±) for LVDS buses C and D can be disabled to reduce the total number of LVDS pins by eight. In this mode, the LVDS bus A data clock (DACLK±) and strobe (DASTR±) can be used with the data from bus C and the same signals for bus B can be used for LVDS bus D. The tradeoff is that digital interface timing may become more difficult. See the Section 7.4.5.3 and Section 7.4.5.4 sections.