7.3.3 Clocking

The ADC12J1600 and ADC12J2700 devices have a differential clock input, DEVCLK+ and DEVCLK–, that must be driven with an AC-coupled differential clock-signal. The clock inputs are internally terminated and biased. The input clock signal must be capacitively coupled to the clock pins as shown in Figure 65.

Figure 65. Differential Sample-Clock Connection

The differential sample-clock line pair must have a characteristic impedance of 100 Ω and must be terminated at the clock source of that 100-Ω characteristic impedance. The input clock line must be as short and direct as possible. The ADC12J1600 and ADC12J2700 clock input is internally terminated with an untrimmed 100-Ω resistance.

Insufficient input clock levels results in poor dynamic performance. Excessively-high input-clock levels can cause a change in the analog-input offset voltage. To avoid these issues, maintain the input clock level within the range specified in the Electrical Characteristics table.

The low times and high times of the input clock signal can affect the performance of any ADC. The ADC12J1600 and ADC12J2700 devices feature a duty-cycle clock-correction circuit which maintains performance over temperature. The ADC meets the performance specification when the input clock high times and low times are maintained as specified in the Electrical Characteristics table.

High-speed high-performance ADCs such as the ADC12J1600 and ADC12J2700 devices require a very-stable input clock-signal with minimum phase noise or jitter. ADC jitter requirements are defined by the ADC resolution or ENOB (effective number of bits), maximum ADC input frequency, and the input signal amplitude relative to the ADC input full-scale range. Use Equation 1 to calculate the maximum jitter (the sum of the jitter from all sources) allowed to prevent a jitter-induced reduction in SNR.

Equation 1.

where

• RMS_tot(J) is the RMS total of all jitter sources in seconds
• V_I(PP) is the peak-to-peak analog input signal
• V_FSR is the full-scale range of the ADC
• n is the ADC resolution in bits
• F_IN is the maximum input frequency, in Hertz, at the ADC analog input

Note that the maximum jitter previously described is the root sum square (RSS) of the jitter from all sources, including that from the clock source, the jitter added by noise coupling at board level and that added internally by the ADC clock circuitry, in addition to any jitter added to the input signal. Because the effective jitter added by the ADC is beyond user control, the best option is to minimize the jitter from the clock source, the sum of the externally-added input clock jitter and the jitter added by any circuitry to the analog signal.

Input clock amplitudes above those specified in the Recommended Operating Conditions table can result in increased input-offset voltage. Increased input-offset voltage causes the converter to produce an output code other than the expected 2048 when both input pins are at the same potential.