ZHCSCX0D January   2014  – October 2017 ADC12J1600 , ADC12J2700

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     旁路 — 频谱响应 ƒS = 2.7GHz，FIN = 1897MHz（–1dBFS 时）
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Internal Characteristics
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Signal Acquisition
      2. 7.3.2 The Analog Inputs
        1. 7.3.2.1 Input Clamp
        2. 7.3.2.2 AC Coupled Input Usage
        3. 7.3.2.3 DC Coupled Input Usage
        4. 7.3.2.4 Handling Single-Ended Input Signals
      3. 7.3.3 Clocking
      4. 7.3.4 Over-Range Function
      5. 7.3.5 ADC Core Features
        1. 7.3.5.1 The Reference Voltage
        2. 7.3.5.2 Common-Mode Voltage Generation
        3. 7.3.5.3 Bias Current Generation
        4. 7.3.5.4 Full Scale Range Adjust
        5. 7.3.5.5 Offset Adjust
        6. 7.3.5.6 Power-Down
        7. 7.3.5.7 Built-In Temperature Monitor Diode
      6. 7.3.6 Digital Down Converter (DDC)
        1. 7.3.6.1 NCO/Mixer
        2. 7.3.6.2 NCO Settings
          1. 7.3.6.2.1 NCO Frequency Phase Selection
          2. 7.3.6.2.2 NCO_0, NCO_1, and NCO_2 (NCO_x)
          3. 7.3.6.2.3 NCO_SEL Bits (2:0)
          4. 7.3.6.2.4 NCO Frequency Setting (Eight Total)
            1. 7.3.6.2.4.1 Basic NCO Frequency-Setting Mode
            2. 7.3.6.2.4.2 Rational NCO Frequency Setting Mode
          5. 7.3.6.2.5 NCO Phase-Offset Setting (Eight Total)
          6. 7.3.6.2.6 Programmable DDC Delay
        3. 7.3.6.3 Decimation Filters
        4. 7.3.6.4 DDC Output Data
        5. 7.3.6.5 Decimation Settings
          1. 7.3.6.5.1 Decimation Factor
          2. 7.3.6.5.2 DDC Gain Boost
      7. 7.3.7 Data Outputs
        1. 7.3.7.1 The Digital Outputs
        2. 7.3.7.2 JESD204B Interface Features and Settings
          1. 7.3.7.2.1  Scrambler Enable
          2. 7.3.7.2.2  Frames Per Multi-Frame (K-1)
          3. 7.3.7.2.3  DDR
          4. 7.3.7.2.4  JESD Enable
          5. 7.3.7.2.5  JESD Test Modes
          6. 7.3.7.2.6  Configurable Pre-Emphasis
          7. 7.3.7.2.7  Serial Output-Data Formatting
          8. 7.3.7.2.8  JESD204B Synchronization Features
          9. 7.3.7.2.9  SYSREF
          10. 7.3.7.2.10 SYNC~
          11. 7.3.7.2.11 Time Stamp
          12. 7.3.7.2.12 Code-Group Synchronization
          13. 7.3.7.2.13 Multiple ADC Synchronization
    4. 7.4 Device Functional Modes
      1. 7.4.1 DDC Bypass Mode
      2. 7.4.2 DDC Modes
      3. 7.4.3 Calibration
        1. 7.4.3.1 Foreground Calibration Mode
        2. 7.4.3.2 Background Calibration Mode
      4. 7.4.4 Timing Calibration Mode
      5. 7.4.5 Test-Pattern Modes
        1. 7.4.5.1 ADC Test-Pattern Mode
        2. 7.4.5.2 Serializer Test-Mode Details
        3. 7.4.5.3 PRBS Test Modes
        4. 7.4.5.4 Ramp Test Mode
        5. 7.4.5.5 Short and Long-Transport Test Mode
        6. 7.4.5.6 D21.5 Test Mode
        7. 7.4.5.7 K28.5 Test Mode
        8. 7.4.5.8 Repeated ILA Test Mode
        9. 7.4.5.9 Modified RPAT Test Mode
    5. 7.5 Programming
      1. 7.5.1 Using the Serial Interface
        1. 7.5.1.1 Streaming Mode
    6. 7.6 Register Map
      1. 7.6.1 Memory Map
      2. 7.6.2 Register Descriptions
        1. 7.6.2.1 Standard SPI-3.0 (0x000 to 0x00F)
          1. Table 40. Standard SPI-3.0 Registers
          2. 7.6.2.1.1  Configuration A Register (address = 0x000) [reset = 0x3C]
            1. Table 41. CFGA Field Descriptions
          3. 7.6.2.1.2  Configuration B Register (address = 0x001) [reset = 0x00]
            1. Table 42. CFGB Field Descriptions
          4. 7.6.2.1.3  Device Configuration Register (address = 0x002) [reset = 0x00]
            1. Table 43. DEVCFG Field Descriptions
          5. 7.6.2.1.4  Chip Type Register (address = 0x003) [reset = 0x03]
            1. Table 44. CHIP_TYPE Field Descriptions
          6. 7.6.2.1.5  Chip Version Register (address = 0x006) [reset = 0x13]
            1. Table 45. CHIP_VERSION Field Descriptions
          7. 7.6.2.1.6  Vendor Identification Register (address = 0x00C to 0x00D) [reset = 0x0451]
            1. Table 46. VENDOR_ID Field Descriptions
        2. 7.6.2.2 User SPI Configuration (0x010 to 0x01F)
          1. 7.6.2.2.1 User SPI Configuration Register (address = 0x010) [reset = 0x00]
            1. Table 48. USR0 Field Descriptions
        3. 7.6.2.3 General Analog, Bias, Band Gap, and Track and Hold (0x020 to 0x02F)
          1. 7.6.2.3.1 Power-On Reset Register (address = 0x021) [reset = 0x00]
            1. Table 50. POR Field Descriptions
          2. 7.6.2.3.2 I/O Gain 0 Register (address = 0x022) [reset = 0x40]
            1. Table 51. IO_GAIN_0 Field Descriptions
          3. 7.6.2.3.3 IO_GAIN_1 Register (address = 0x023) [reset = 0x00]
            1. Table 52. IO_GAIN_1 Field Descriptions
          4. 7.6.2.3.4 I/O Offset 0 Register (address = 0x025) [reset = 0x40]
            1. Table 53. IO_OFFSET_0 Field Descriptions
          5. 7.6.2.3.5 I/O Offset 1 Register (address = 0x026) [reset = 0x00]
            1. Table 54. IO_OFFSET_1 Field Descriptions
        4. 7.6.2.4 Clock (0x030 to 0x03F)
          1. 7.6.2.4.1 Clock Generator Control 0 Register (address = 0x030) [reset = 0xC0]
            1. Table 56. CLKGEN_0 Field Descriptions
          2. 7.6.2.4.2 Clock Generator Status Register (address = 0x031) [reset = 0x07]
            1. Table 57. CLKGEN_1 Field Descriptions
          3. 7.6.2.4.3 Clock Generator Control 2 Register (address = 0x032) [reset = 0x80]
            1. Table 58. CLKGEN_2 Field Descriptions
          4. 7.6.2.4.4 Analog Miscellaneous Register (address = 0x033) [reset = 0xC3]
            1. Table 59. ANA_MISC Field Descriptions
          5. 7.6.2.4.5 Input Clamp Enable Register (address = 0x034) [reset = 0x2F]
            1. Table 60. IN_CL_EN Field Descriptions
        5. 7.6.2.5 Serializer (0x040 to 0x04F)
          1. 7.6.2.5.1 Serializer Configuration Register (address = 0x040) [reset = 0x04]
            1. Table 62. SER_CFG Field Descriptions
        6. 7.6.2.6 ADC Calibration (0x050 to 0x1FF)
          1. 7.6.2.6.1 Calibration Configuration 0 Register (address = 0x050) [reset = 0x06]
            1. Table 64. CAL_CFG0 Field Descriptions
          2. 7.6.2.6.2 Calibration Configuration 1 Register (address = 0x051) [reset = 0xF4]
            1. Table 65. CAL_CFG1 Field Descriptions
          3. 7.6.2.6.3 Calibration Background Control Register (address = 0x057) [reset = 0x10]
            1. Table 66. CAL_BACK Field Descriptions
          4. 7.6.2.6.4 ADC Pattern and Over-Range Enable Register (address = 0x058) [reset = 0x00]
            1. Table 67. ADC_PAT_OVR_EN Field Descriptions
          5. 7.6.2.6.5 Calibration Vectors Register (address = 0x05A) [reset = 0x00]
            1. Table 68. CAL_VECTOR Field Descriptions
          6. 7.6.2.6.6 Calibration Status Register (address = 0x05B) [reset = undefined]
            1. Table 69. CAL_STAT Field Descriptions
          7. 7.6.2.6.7 Timing Calibration Register (address = 0x066) [reset = 0x02]
            1. Table 70. CAL_STAT Field Descriptions
        7. 7.6.2.7 Digital Down Converter and JESD204B (0x200-0x27F)
          1. 7.6.2.7.1  Digital Down-Converter (DDC) Control Register (address = 0x200) [reset = 0x10]
            1. Table 72. DDC_CTRL1 Field Descriptions
          2. 7.6.2.7.2  JESD204B Control 1 Register (address = 0x201) [reset = 0x0F]
            1. Table 73. JESD_CTRL1 Field Descriptions
          3. 7.6.2.7.3  JESD204B Control 2 Register (address = 0x202) [reset = 0x00]
            1. Table 74. JESD_CTRL2 Field Descriptions
          4. 7.6.2.7.4  JESD204B Device ID (DID) Register (address = 0x203) [reset = 0x00]
            1. Table 75. JESD_DID Field Descriptions
          5. 7.6.2.7.5  JESD204B Control 3 Register (address = 0x204) [reset = 0x00]
            1. Table 76. JESD_CTRL3 Field Descriptions
          6. 7.6.2.7.6  JESD204B and System Status Register (address = 0x205) [reset = Undefined]
            1. Table 77. JESD_STATUS Field Descriptions
          7. 7.6.2.7.7  Overrange Threshold 0 Register (address = 0x206) [reset = 0xF2]
            1. Table 78. OVR_T0 Field Descriptions
          8. 7.6.2.7.8  Overrange Threshold 1 Register (address = 0x207) [reset = 0xAB]
            1. Table 79. OVR_T1 Field Descriptions
          9. 7.6.2.7.9  Overrange Period Register (address = 0x208) [reset = 0x00]
            1. Table 80. OVR_N Field Descriptions
          10. 7.6.2.7.10 DDC Configuration Preset Mode Register (address = 0x20C) [reset = 0x00]
            1. Table 81. NCO_MODE Field Descriptions
          11. 7.6.2.7.11 DDC Configuration Preset Select Register (address = 0x20D) [reset = 0x00]
            1. Table 82. NCO_SEL Field Descriptions
          12. 7.6.2.7.12 Rational NCO Reference Divisor Register (address = 0x20E to 0x20F) [reset = 0x0000]
            1. Table 83. NCO_RDIV Field Descriptions
          13. 7.6.2.7.13 NCO Frequency (Preset x) Register (address = see ) [reset = see ]
            1. Table 84. NCO_FREQ_x Field Descriptions
          14. 7.6.2.7.14 NCO Phase (Preset x) Register (address = see ) [reset = see ]
            1. Table 85. NCO_PHASE_x Field Descriptions
          15. 7.6.2.7.15 DDC Delay (Preset x) Register (address = see ) [reset = see ]
            1. Table 86. DDC_DLY_x Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 RF Sampling Receiver
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Oscilloscope
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
    3. 8.3 Initialization Set-Up
      1. 8.3.1 JESD204B Startup Sequence
    4. 8.4 Dos and Don'ts
      1. 8.4.1 Common Application Pitfalls
  9. 9 Power Supply Recommendations
    1. 9.1 Supply Voltage
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Management
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 开发支持
      3. 11.1.3 器件命名规则
    2. 11.2 文档支持
      1. 11.2.1 相关文档
    3. 11.3 相关链接
    4. 11.4 社区资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.3.7.2.7 Serial Output-Data Formatting

Output data is generated by the DDC then formatted according to the selected decimation and output rate settings. When less than the maximum of eight lanes are active, lanes are disabled beginning with the highest numerical lanes. For example when only two lanes are active, lanes 0 and 1 are active, while all higher lanes are inactive.

Table 10. Parameter Definitions

PARAMETERDESCRIPTIONUSER CONFIGURED OR DERIVEDSTANDARD JESD204B LINK PARAMETER
D Decimation factor, determined by DMODE register User No
DDR Serial line rate: 1 = DDR rate (2x), 0 = SDR rate (1x) User No
P54 Enable 5/4 PLL to increase line rate by 1.25x. User No 
0 = no PLL (1x), 1 = enable PLL (1.25x)
K Number of frames per multiframe User Yes
N Bits per sample (before adding control bits and tails bits) Derived Yes
CS Control bits per sample Derived Yes
N’ Bits per sample (after adding control bits and tail bits). Must be a multiple of 4. Derived Yes
L Number of serial lanes Derived Yes
F Number of octets (bytes) per frame (per lane) Derived Yes
M Number of (logical) converters Derived Yes
S Number of samples per converter per frame Derived Yes
CF Number of control words per frame Derived Yes
HD 1=High density mode (samples may be broken across lanes), 0 = normal mode (samples may not be broken across lanes) Derived Yes
KS Legal adjustment step for K, to ensure that the multi-frame clock is a sub-harmonic of other internal clocks Derived No

Table 11. Serial Link Parameters(1)

USER SPECIFIED PARAMETERSDERIVED PARAMETERSOTHER INFORMATION
DECIMATION FACTOR (D)DDRP54NCSN’LFMSKSLEGAL K RANGEBIT RATE / ADC CLOCK(2)
1 1 0 12 0 12 8 8 8 5 2 4-32 2x
4 1 0 15 1 16 5 4 2 5 4 8-32 2x
4 1 1 15 1 16 4 2 2 2 2 10-32 2.5x 
8 0 0 15 1 16 5 4 2 5 2 6-32 1x
8 0 1 15 1 16 4 2 2 2 1 9-32 1.25x 
8 1 0 15 1 16 3 8 2 5 2 4-32 2x
8 1 1 15 1 16 2 2 2 1 2 10-32 2.5x 
10 0 0 15 1 16 4 2 2 2 4 12-32 1x
10 1 0 15 1 16 2 2 2 1 8 16-32 2x
16 0 0 15 1 16 3 8 2 5 1 3-32 1x
16 0 1 15 1 16 2 2 2 1 1 9-32 1.25x 
16 1 0 15 1 16 2 16 2 5 1 2-32 2x
16 1 1 15 1 16 1 4 2 1 1 5-32 2.5x 
20 0 0 15 1 16 2 2 2 1 4 12-32 1x
20 1 0 15 1 16 1 4 2 1 4 8-32 2x
32 0 0 15 1 16 2 16 2 5 1 2-32 1x
32 0 1 15 1 16 1 4 2 1 1 5-32 1.25x 
32 1 0 15 1 16 1 32 2 5 1 1-32 2x
(1) In all modes: HD = 0 and CF = 0
(2) x = times (for example, 2x = 2-times)

Output data is formatted in a specific optimized fashion for each decimation and DDR setting combination. For bypass mode (decimation = 1) the 12-bit offset binary values are mapped to the 8-bit characters. For the DDC mode the 16-bit values (15-bit complex data plus 1 bit OR_Tn) are mapped to the 8-bit characters. The following tables list the specific mapping formats. In all mappings the T or tail bits are 0 (zero).

Table 12. Bypass Mode, No Decimation, DDR = 1, P54 = 0, LMF = 8,8,8

TIME →
CHAR NUMBER01234567
Lane 0 C0S0 C0S1 C0S2 C0S3 C0S4 T
Lane 1 C1S0 C1S1 C1S2 C1S3 C1S4 T
Lane 2 C2S0 C2S1 C2S2 C2S3 C2S4 T
Lane 3 C3S0 C3S1 C3S2 C3S3 C3S4 T
Lane 4 C4S0 C4S1 C4S2 C4S3 C4S4 T
Lane 5 C5S0 C5S1 C5S2 C5S3 C5S4 T
Lane 6 C6S0 C6S1 C6S2 C6S3 C6S4 T
Lane 7 C7S0 C7S1 C7S2 C7S3 C7S4 T
Frame n

Table 13. Bypass Mode, No Decimation, DDR = 1, P54 = 0, Composite View of Interleaved Converters

TIME →
CHAR NUMBER01234567
Lane 0 S0 S8 S16 S24 S32 T
Lane 1 S1 S9 S17 S25 S33 T
Lane 2 S2 S10 S18 S26 S34 T
Lane 3 S3 S11 S19 S27 S35 T
Lane 4 S4 S12 S20 S28 S36 T
Lane 5 S5 S13 S21 S29 S37 T
Lane 6 S6 S14 S22 S30 S38 T
Lane 7 S7 S15 S23 S31 S39 T
Frame n

Table 14. Decimate-by-4, DDR = 1, P54 = 0, LMF = 5,2,4

TIME →
CHAR NUMBER0123
Lane 0 I0 I1
Lane 1 I2 I3
Lane 2 I4 Q0
Lane 3 Q1 Q2
Lane 4 Q3 Q4
Frame n

Table 15. Decimate-by-4, DDR = 1, P54 = 1, LMF = 4,2,2

TIME →
CHAR NUMBER012345
Lane 0 I0 I2 I4
Lane 1 I1 I3 I5
Lane 2 Q0 Q2 Q4
Lane 3 Q1 Q3 Q5
Frame
n		 Frame
n + 1		 Frame
n + 2

Table 16. Decimate-by-8, DDR = 0, P54 = 0, LMF = 5,2,4

TIME →
CHAR NUMBER0123
Lane 0 I0 I1
Lane 1 I2 I3
Lane 2 I4 Q0
Lane 3 Q1 Q2
Lane 4 Q3 Q4
Frame n

Table 17. Decimate-by-8, DDR = 0, P54 = 1, LMF = 4,2,2

TIME →
CHAR NUMBER012345
Lane 0 I0 I2 I4
Lane 1 I1 I3 I5
Lane 2 Q0 Q2 Q4
Lane 3 Q1 Q3 Q5
Frame
n		 Frame
n + 1		 Frame
n + 2

Table 18. Decimate-by-8, DDR = 1, P54 = 0, LMF = 3,2,8

TIME →
CHAR NUMBER01234567
Lane 0 I0 I1 I2 I3
Lane 1 I4 Q0 Q1 Q2
Lane 2 Q3 Q4 T T
Frame n

Table 19. Decimate-by-8, DDR = 1, P54=1, LMF = 2,2,2

TIME →
CHAR NUMBER012345
Lane 0 I0 I1 I2
Lane 1 Q0 Q1 Q2
Frame
n		 Frame
n + 1		 Frame
n + 2

Table 20. Decimate-by-10, DDR = 0, P54 = 0, LMF = 4,2,2

TIME →
CHAR NUMBER01234567
Lane 0 I0 I2 I4 I6
Lane 1 I1 I3 I5 I7
Lane 2 Q0 Q2 Q4 Q6
Lane 3 Q1 Q3 Q5 Q7
Frame
n		 Frame
n + 1		 Frame
n + 2		 Frame
n + 3

Table 21. Decimate-by-10, DDR = 1, P54 = 0, LMF = 2,2,2

TIME →
CHAR NUMBER01234567
Lane 0 I0 I1 I2 I3
Lane 1 Q0 Q1 Q2 Q3
Frame
n		 Frame
n + 1		 Frame
n + 2		 Frame
n+3

Table 22. Decimate-by-16, DDR = 0, P54 = 0, LMF = 3,2,8

TIME →
CHAR NUMBER01234567
Lane 0 I0 I1 I2 I3
Lane 1 I4 Q0 Q1 Q2
Lane 2 Q3 Q4 T T
Frame n

Table 23. Decimate-by-16, DDR = 0, P54 = 1, LMF = 2,2,2

TIME →
CHAR NUMBER012345
Lane 0 I0 I1 I2
Lane 1 Q0 Q1 Q2
Frame
n		 Frame
n + 1		 Frame
n + 2

Table 24. Decimate-by-16, DDR = 1, P54 = 0, LMF = 2,2,16

TIME →
CHAR NUMBER0123456789101112131415
Lane 0 I0 I1 I2 I3 I4 Q0 Q1 Q2
Lane 1 Q3 Q4 T T T T T T
Frame n

Table 25. Decimate-by-16, DDR = 1, P54 = 1, LMF = 1,2,4

TIME →
CHAR NUMBER01234567891011
Lane 0 I0 Q0 I1 Q1 I2 Q2
Frame n Frame n + 1 Frame n + 2

Table 26. Decimate-by-20, DDR = 0, P54 = 0, LMF = 2,2,2

TIME →
CHAR NUMBER01234567
Lane 0 I0 I1 I2 I3
Lane 1 Q0 Q1 Q2 Q3
Frame
n		 Frame
n + 1		 Frame
n + 2		 Frame
n + 3

Table 27. Decimate-by-20, DDR = 1, P54 = 0, LMF = 1,2,2

TIME →
CHAR NUMBER01234567
Lane 0 I0 Q0 I1 Q1
Frame n Frame n + 1

Table 28. Decimate-by-32, DDR = 0, P54 = 0, LMF = 2,2,16

TIME →
CHAR NUMBER0123456789101112131415
Lane 0 I0 I1 I2 I3 I4 Q0 Q1 Q2
Lane 1 Q3 Q4 T T T T T T
Frame n

Table 29. Decimate-by-32, DDR = 0, P54 = 1, LMF = 1,2,4

TIME →
CHAR NUMBER01234567891011
Lane 0 I0 Q0 I1 Q1 I2 Q2
Frame n Frame n + 1 Frame n + 2

Table 30. Decimate-by-32, DDR = 1, P54 = 0, LMF = 1,2,32

TIME →
CHAR NUMBER012345678910111213141516171819202122232425262728293031
Lane 0 I0 I1 I2 I3 I4 Q0 Q1 Q2 Q3 Q4 T T T T T T
Frame n

The formatted data is 8b10b encoded and output on the serial lanes. The 8b10b encoding provides a number of specific benefits, including:

  • Standard encoding format. Therefore the IP is readily available in off-the-shelf FPGAs and ASIC building blocks.
  • Inherent DC balance allows AC coupling of lanes with small on-chip capacitors
  • Inherent error checking
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