米6体育平台手机版

ZHCSCX1D January 2014 – October 2017 ADC12J4000

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

NKE|68
- MPQS033A

散热焊盘机械数据 (封装 | 引脚)

订购信息

6.5 Electrical Characteristics

Unless otherwise noted, these specifications apply for V_(VA12) = V_(VD12) = 1.2 V, V_(VA19) = 1.9 V, VIN full scale range at default setting (725 mV_PP), VIN = –1 dBFS, differential AC-coupled sinewave input clock, ƒ_(DEVCLK) = 4 GHz at 0.5 V_PP with 50% duty cycle, R_(RBIAS) = 3.3 kΩ ±0.1%, after a foreground (FG) mode calibration with timing calibration enabled. Typical values are at T_A = 25°C.⁽¹⁾⁽³⁾

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
DYNAMIC PERFORMANCE CHARACTERISTICS
RES	ADC core resolution	Resolution with no missing codes			12		Bits
INL	Integral non-linearity	T_A = 25°C			±2		LSB
INL	Integral non-linearity	T_A = T_MIN to T_MAX			±3		LSB
DNL	Differential non-linearity	T_A = 25°C			±0.25		LSB
DNL	Differential non-linearity	T_A = T_MIN to T_MAX			±0.3		LSB
Peak NPR	Peak noise power ratio	500-kHz tone spacing from 1 MHz to ƒ_S / 2−1 MHz, DDC bypass mode 25-MHz wide notch at 320 MHz			46		dB
IMD₃	Third-order intermodulation distortion	F1 = 2110 MHz at −13 dBFS F2 = 2170 MHz at −13 dBFS			–64		dBc
DDC BYPASS MODE
SNR1	Signal-to-noise ratio, integrated across entire Nyquist bandwidth Input frequency-dependent interleaving spurs included	F_IN = 350 MHz, –1 dBFS, 12-bit DDC bypass mode			55		dBFS
		F_IN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode	T_A = 25°C		54.8
			T_A = T_MIN to T_MAX	52.5
			T_A = 25°C, calibration = BG		53.9
			T_A = T_MIN to T_MAX, calibration = BG	49.4
		F_IN = 1500 MHz, –1 dBFS, 12-bit DDC bypass mode			51.2
		F_IN = 2400 MHz, –1 dBFS, 12-bit DDC bypass mode			48.7
SNR2	Signal-to-noise ratio, integrated across entire Nyquist bandwidth Input frequency-dependent interleaving spurs excluded	F_IN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode	T_A = 25°C⁽⁴⁾		55		dBFS
			T_A = T_MIN to T_MAX⁽⁴⁾	53
			T_A = 25°C, calibration = BG⁽⁴⁾		55
			T_A = T_MIN to T_MAX, calibration = BG⁽⁴⁾	53
SINAD1	Signal-to-noise and distortion ratio, integrated across entire Nyquist bandwidth Input frequency-dependent interleaving spurs included	F_IN = 350 MHz, –1 dBFS, 12-bit DDC bypass mode			54.8		dBFS
		F_IN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode	T_A = 25°C		54.7
			T_A = T_MIN to T_MAX	52.3
			T_A = 25°C, calibration = BG		53.8
			T_A = T_MIN to T_MAX, calibration = BG	49.2
		F_IN = 1500 MHz, –1 dBFS, 12-bit DDC bypass mode			51.1
		F_IN = 2400 MHz, –1 dBFS, 12-bit DDC bypass mode			48.7
SINAD2	Signal-to-noise and distortion ratio, integrated across DDC output bandwidth Input frequency-dependent interleaving spurs excluded	F_IN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode	T_A = 25°C⁽⁴⁾		54.9		dBFS
			T_A = T_MIN to T_MAX⁽⁴⁾	52.7
			T_A = 25°C, calibration = BG⁽⁴⁾		54.9
			T_A = T_MIN to T_MAX, calibration = BG⁽⁴⁾	52.7
ENOB1	Effective number of bits, integrated across entire Nyquist bandwidth Input frequency-dependent interleaving spurs included	F_IN = 350 MHz, –1 dBFS, 12-bit DDC bypass mode			8.8		Bits
		F_IN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode	T_A = 25°C		8.8
			T_A = T_MIN to T_MAX	8.4
			T_A = 25°C, calibration = BG		8.7
			T_A = T_MIN to T_MAX, calibration = BG	7.9
		F_IN = 1500 MHz, –1 dBFS, 12-bit DDC bypass mode			8.2
		F_IN = 2400 MHz, –1 dBFS, 12-bit DDC bypass mode			7.8
ENOB2	Effective number of bits, integrated across entire Nyquist bandwidth Input frequency-dependent interleaving spurs excluded	F_IN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode	T_A = 25°C⁽⁴⁾		8.8		Bits
			T_A = T_MIN to T_MAX⁽⁴⁾	8.5
			T_A = 25°C, calibration = BG⁽⁴⁾		8.8
			T_A = T_MIN to T_MAX, calibration = BG⁽⁴⁾	8.5
SFDR1	Spurious-free dynamic range Input frequency-dependent interleaving spurs included	F_IN = 350 MHz, –1 dBFS, 12-bit DDC bypass mode			67.4		dBFS
		F_IN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode	T_A = 25°C		70.7
			T_A = T_MIN to T_MAX	60
			T_A = 25°C, calibration = BG		63.4
			T_A = T_MIN to T_MAX, calibration = BG	51.8
		F_IN = 1500 MHz, –1 dBFS, 12-bit DDC bypass mode			59.8
		F_IN = 2400 MHz, –1 dBFS, 12-bit DDC bypass mode			57.2
SFDR2	Spurious-free dynamic range Input frequency-dependent interleaving spurs excluded	F_IN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode	T_A = 25°C⁽⁴⁾		73		dBFS
			T_A = T_MIN to T_MAX⁽⁴⁾	61.6
			T_A = 25°C, calibration = BG⁽⁴⁾		74
			T_A = T_MIN to T_MAX, calibration = BG ⁽⁴⁾mode	62.8
ƒ_S/2	Interleaving offset spur at ½ sampling rate	F_IN = 350 MHz, –1 dBFS, 12-bit DDC bypass mode			–75		dBFS
		F_IN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode	T_A = 25°C		–76
			T_A = T_MIN to T_MAX			–60
			T_A = 25°C, calibration = BG		–68
			T_A = T_MIN to T_MAX, calibration = BG			–55
		F_IN = 1500 MHz, –1 dBFS, 12-bit DDC bypass mode			–75
		F_IN = 2400 MHz, –1 dBFS, 12-bit DDC bypass mode			–75
ƒ_S/4	Interleaving offset spur at ¼ sampling rate	F_IN = 350 MHz, –1 dBFS, 12-bit DDC bypass mode			–68		dBFS
		F_IN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode	T_A = 25°C		–70
			T_A = T_MIN to T_MAX			–55
			T_A = 25°C, calibration = BG		–61
			T_A = T_MIN to T_MAX, calibration = BG			–47.4
		F_IN = 1500 MHz, –1 dBFS, 12-bit DDC bypass mode			–68
		F_IN = 2400 MHz, –1 dBFS, 12-bit DDC bypass mode			–68
ƒ_S/2 – F_IN	Interleaving offset spur at ½ sampling rate – input frequency	F_IN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode	T_A = 25°C		–77		dBFS
			T_A = T_MIN to T_MAX			–61.7
			T_A = 25°C, calibration = BG		–70
			T_A = T_MIN to T_MAX, calibration = BG			–51.9
ƒ_S/4 + F_IN	Interleaving offset spur at ¼ sampling rate + input frequency	F_IN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode	T_A = 25°C		–74		dBFS
			T_A = T_MIN to T_MAX			–60
			T_A = 25°C, calibration = BG		–66
			T_A = T_MIN to T_MAX, calibration = BG			–52
ƒ_S/4 – F_IN	Interleaving offset spur at ¼ sampling rate – input frequency	F_IN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode	T_A = 25°C		–76		dBFS
			T_A = T_MIN to T_MAX			–60.4
			T_A = 25°C, calibration = BG		–67
			T_A = T_MIN to T_MAX, calibration = BG			–53.3
THD	Total harmonic distortion	F_IN = 350 MHz, –1 dBFS, 12-bit DDC bypass mode			–72		dBFS
		F_IN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode	T_A = 25°C		–70
			T_A = T_MIN to T_MAX			–60
			T_A = 25°C, calibration = BG		–72
			T_A = T_MIN to T_MAX, calibration = BG			–60
		F_IN = 1500 MHz, –1 dBFS, 12-bit DDC bypass mode			–68
		F_IN = 2400 MHz, –1 dBFS, 12-bit DDC bypass mode			–74
HD2	Second harmonic distortion	F_IN = 350 MHz, –1 dBFS, 12-bit DDC bypass mode			–85		dBFS
		F_IN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode	T_A = 25°C		–80
			T_A = T_MIN to T_MAX			–62
			T_A = 25°C, calibration = BG		–80
			T_A = T_MIN to T_MAX, calibration = BG			–62.5
		F_IN = 1500 MHz, –1 dBFS, 12-bit DDC bypass mode			–71
		F_IN = 2400 MHz, –1 dBFS, 12-bit DDC bypass mode			–79
HD3	Third harmonic distortion	F_IN = 350 MHz, –1 dBFS, 12-bit DDC bypass mode			–73		dBFS
		F_IN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode	T_A = 25°C		–75
			T_A = T_MIN to T_MAX			–61
			T_A = 25°C, calibration = BG		–80
			T_A = T_MIN to T_MAX, calibration = BG			–61.7
		F_IN = 1500 MHz, –1 dBFS, 12-bit DDC bypass mode			–74
		F_IN = 2400 MHz, –1 dBFS, 12-bit DDC bypass mode			–76
NSD	Noise spectral density, average NSD across Nyquist bandwidth	12-bit DDC bypass mode	50-Ω AC-coupled terminated input		–149		dBFS/Hz
			50-Ω AC-coupled terminated input		–150.8		dBm/Hz
			F_IN = 600 MHz, –1 dBFS		–147.8		dBFS/Hz
			F_IN = 600 MHz, –1 dBFS		–149.6		dBm/Hz
DECIMATE-BY-8 MODE
SNR1	Signal-to-noise ratio, integrated across DDC output bandwidth Interleaving spurs included	F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode			63		dBFS
		F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode	Calibration = BG		61.6
		F_IN = 2400 MHz, –1 dBFS, decimate-by-8 mode			54.6
SNR2	Signal-to-noise ratio, integrated across DDC output bandwidth Interleaving spurs excluded	F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode⁽⁴⁾			63.3		dBFS
SNR2		F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode⁽⁴⁾	Calibration = BG		63.3		dBFS
SINAD1	Signal-to-noise and distortion ratio, integrated across DDC output bandwidth Interleaving spurs included	F_IN = 600 MHz, –1 dBFS, Decimate-by-8 mode			63		dBFS
		F_IN = 600 MHz, –1 dBFS, Decimate-by-8 mode	Calibration = BG		61.6
		F_IN = 2400 MHz, –1 dBFS, decimate-by-8 mode			54.6
SINAD2	Signal-to-noise and distortion ratio, integrated across DDC output bandwidth Interleaving spurs excluded	F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode⁽⁴⁾			63.3		dBFS
SINAD2		F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode⁽⁴⁾	Calibration = BG		63.3		dBFS
ENOB1	Effective number of bits, integrated across DDC output bandwidth Interleaving spurs included	F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode			10.2		Bits
		F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode	Calibration = BG		10.0
		F_IN = 2400 MHz, –1 dBFS, decimate-by-8 mode			8.8
ENOB2	Effective number of bits, integrated across DDC output bandwidth Interleaving spurs excluded	F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode⁽⁵⁾			10.2		Bits
ENOB2		F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode⁽⁵⁾	Calibration = BG		10.2		Bits
SFDR1	Spurious-free dynamic range Interleaving Spurs Included	F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode			74.9		dBFS
SFDR1	Spurious-free dynamic range Interleaving Spurs Included	F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode	Calibration = BG		68.3		dBFS
SFDR2	Spurious-free dynamic range Interleaving spurs excluded	F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode⁽⁵⁾			77.8		dBFS
SFDR2	Spurious-free dynamic range Interleaving spurs excluded	F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode⁽⁵⁾	Calibration = BG		77.8		dBFS
ƒ_S/2	Interleaving offset spur at ½ sampling rate⁽⁵⁾	F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode			–73		dBFS
ƒ_S/2	Interleaving offset spur at ½ sampling rate⁽⁵⁾	F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode	Calibration = BG		–72		dBFS
ƒ_S/4	Interleaving offset spur at ¼ sampling rate⁽⁵⁾	F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode			–70		dBFS
ƒ_S/4	Interleaving offset spur at ¼ sampling rate⁽⁵⁾	F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode	Calibration = BG		–66		dBFS
ƒ_S/2 – F_IN	Interleaving spur at ½ sampling rate – input frequency⁽⁵⁾	F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode			–76		dBFS
ƒ_S/2 – F_IN	Interleaving spur at ½ sampling rate – input frequency⁽⁵⁾	F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode	Calibration = BG		–67		dBFS
ƒ_S/4 + F_IN	Interleaving spur at ¼ sampling rate + input frequency⁽⁵⁾	F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode			–72		dBFS
ƒ_S/4 + F_IN	Interleaving spur at ¼ sampling rate + input frequency⁽⁵⁾	F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode	Calibration = BG		–64		dBFS
ƒ_S/4 – F_IN	Interleaving spur at ¼ sampling rate – input frequency⁽⁵⁾	F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode			–74		dBFS
ƒ_S/4 – F_IN	Interleaving spur at ¼ sampling rate – input frequency⁽⁵⁾	F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode	Calibration = BG		–67		dBFS
THD	Total harmonic distortion⁽⁶⁾	F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode			–70		dBFS
		F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode	Calibration = BG		–72
		F_IN = 2400 MHz, –1 dBFS, decimate-by-8 mode			–71
HD2	Second harmonic distortion⁽⁶⁾	F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode			–80		dBFS
		F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode	Calibration = BG		–79
		F_IN = 2400 MHz, –1 dBFS, decimate-by-8 mode			–78
HD3	Third harmonic distortion⁽⁶⁾	F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode			–74		dBFS
		F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode	Calibration = BG		–80
		F_IN = 2400 MHz, –1 dBFS, decimate-by-8 mode			–-77
DDC CHARACTERISTICS
	Alias protection⁽²⁾			80			dB
	Alias protected bandwidth⁽²⁾			80			% of output BW
SFDR-DDC	Spurious-free dynamic range of digital down-converter⁽²⁾			100			dB
	Implementation loss⁽²⁾					0.5	dB
ANALOG INPUT CHARACTERISTICS
V_ID(VIN)	Full-scale analog-differential input range	Minimum FSR setting⁽⁶⁾			500		mV_PP
		Default FSR setting, T_A = T_MIN to T_MAX		650	725	800
		Maximum FSR setting⁽⁶⁾			950
C_I(VIN)	Analog input capacitance⁽²⁾	Differential			0.05		pF
C_I(VIN)	Analog input capacitance⁽²⁾	Each input pin to ground			1.5		pF
R_ID(VIN)	Differential input resistance			80	95	110	Ω
FPBW	Full power bandwidth	–3 dB — calibration = BG			2.8		GHz
FPBW	Full power bandwidth	–3 dB — calibration = FG			3.2		GHz
	Gain flatness	DC to 2 GHz			1.2		dB
		2 GHz to 4 GHz			3.8
		DC to 2 GHz — calibration = BG			1.5
		2 GHz to 4 GHz — calibration = BG			4.5
ANALOG OUTPUT CHARACTERISTICS (VCMO, VBG)
V_(VCMO)	Common-mode output voltage	I_(VCMO) = ±100 µA, T_A = 25°C			1.225		V
V_(VCMO)	Common-mode output voltage	I_(VCMO) = ±100 µA, T_A = T_MIN to T_MAX		1.185		1.265	V
TCV_O(VCMO)	Common-mode output-voltage temperature coefficient	T_A = T_MIN to T_MAX			-21		ppm/°C
C_{(LOAD_VCMO)}	Maximum VCMO output load capacitance					80	pF
V_O(BG)	Bandgap reference output voltage	I_(BG) = ±100 µA, T_A = 25°C			1.248		V
V_O(BG)	Bandgap reference output voltage	I_(BG) = ±100 µA, T_A = T_MIN to T_MAX		1.195		1.3	V
TCV_ref(BG)	Bandgap reference voltage temperature coefficient	T_A = T_MIN to T_MAX, I_(BG) = ±100 µA			0		ppm/°C
C_{(LOAD_BG)}	Maximum bandgap reference output load capacitance					80	pF
TEMPERATURE DIODE CHARACTERISTICS
V_(TDIODE)	Temperature diode voltage slope	Offset voltage (approx. 0.77 V) varies with process and must be measured for each part. Offset measurement should be done with PowerDown=1 to minimize device self-heating.	100-µA forward current Device active		–1.6		mV/°C
V_(TDIODE)	Temperature diode voltage slope		100-µA forward current Device in power-down		–1.6		mV/°C
CLOCK INPUT CHARACTERISTICS (DEVCLK±, SYSREF±, SYNC~/TMST±)
V_ID(CLK)	Differential clock input level	Sine wave clock, T_A = T_MIN to T_MAX		0.4	0.6	2	V_PP
V_ID(CLK)	Differential clock input level	Square wave clock, T_A = T_MIN to T_MAX		0.4	0.6	2	V_PP
I_I(CLK)	Input current	V_I = 0 or V_I = V_A			±1		µA
C_I(CLK)	Input capacitance⁽²⁾	Differential			0.02		pF
C_I(CLK)	Input capacitance⁽²⁾	Each input to ground			1		pF
R_ID(CLK)	Differential input resistance	T_A = 25°C			95		Ω
R_ID(CLK)	Differential input resistance	T_A = T_MIN to T_MAX		80		110	Ω
CML OUTPUT CHARACTERISTICS (DS0–DS7±)
V_OD	Differential output voltage	Assumes ideal 100-Ω load Measured differentially Default pre-emphasis setting		280	305	330	mV peak
V_O(ofs)	Output offset voltage				0.6		V
I_OS	Output short-circuit current	Output+ and output– shorted together			±6		mA
I_OS	Output short-circuit current	Output+ or output– shorted to 0 V			12		mA
Z_OD	Differential output impedance				100		Ω
LVCMOS INPUT CHARACTERISTICS (SDI, SCLK, SCS, SYNC~)
V_IH	Logic high input voltage	See ⁽⁶⁾		0.83			V
V_IL	Logic low input voltage	See ⁽⁶⁾				0.4	V
C_I	Input capacitance⁽²⁾⁽⁷⁾	Each input to ground			1		pF
LVCMOS OUTPUT CHARACTERISTICS (SDO, OR_T0, OR_T1)
V_OH	CMOS H level output	I_OH = –400 µA⁽⁶⁾		1.65	1.9		V
V_OL	CMOS L level output	I_OH = 400 µA⁽⁶⁾			0.01	0.15	V
POWER SUPPLY CHARACTERISTICS
I_(VA19)	Analog 1.9-V supply current	PD = 0, calibration = FG, bypass DDC			461	500	mA
		PD = 0, calibration = BG, bypass DDC			560	600
		PD = 0, calibration = BG, decimate by 8, DDR = 0, P54 = 1			560	607
I_(VA12)	Analog 1.2-V supply current	PD = 0, calibration = FG, bypass DDC			320	385	mA
		PD = 0, calibration = BG, bypass DDC			364	420
		PD = 0, calibration = BG, decimate by 8, DDR = 0, P54 = 1			377	428
I_(VD12)	Digital 1.2-V supply current	PD = 0, calibration = FG, bypass DDC			445	710	mA
		PD = 0, calibration = BG, bypass DDC			458	732
		PD = 0, calibration = BG, decimate by 8, DDR = 0, P54 = 1			541	826
P_C	Power consumption	PD = 0, calibration = FG, bypass DDC			1.8	2.26	W
		PD = 0, calibration = BG, bypass DDC			2.05	2.52
		PD = 0, calibration = BG, decimate by 8, DDR = 0, P54 = 1			2.17	2.66
		PD = 1			< 50		mW

(1) To ensure accuracy, the VA19, VA12, and VD12 pins are required to be well bypassed. Each supply pin must be decoupled with one or more bypass capacitors.

(2) This parameter is specified by design and is not tested in production.

(3) Interleave related fixed frequency spurs at ƒ_S / 4 and ƒ_S / 2 are excluded from all SNR, SINAD, ENOB and SFDR specifications. The magnitude of these spurs is provided separately.

(4) Interleave related spurs at ƒ_S / 2 – F_IN, ƒ_S / 4 + F_IN and ƒ_S / 4 – F_IN are excluded from these performance calculations. The magnitude of these spurs is provided separately.

(5) Magnitude of reported tones in output spectrum of ADC core. This tone will only be present in the DDC output for specific Decimation and NCO settings. Careful frequency planning can be used to intentionally place unwanted tones outside the DDC output spectrum.

(6) This parameter is specified by design, characterization, or both and is not tested in production.

(7) The digital control pin capacitances are die capacitances only and is in addition to package and bond-wire capacitance of approximately 0.4 pF.