Additional CMOS PLL reference clock outputs are available on ORC and ORD when configured through CLKCFG[1:0] or through SPI. The clock outputs are available at device power up when CLKCFG[1:0] are used to enable the clock outputs and when PD is held low. Setting the PD pin high disables these outputs; and therefore, the PD pin should not be used when these clocks are necessary for system operation. SPI register overrides are available for the CLKCFG[1:0] pins through the DIVREF_C_MODE and DIVREF_D_MODE SPI register settings. Note that CLKCFG[1:0] can be used to enable or disable ORC and ORD and set the output divider for ORC, but cannot set the output divider for ORD (enable or disable only). The DIVREF_C and DIVREF_D functionality has higher priority than over-range as reflected in Table 6-4 and Table 6-5. Using these outputs as clock outputs results in spurs in the ADC output spectrum at the output frequency and harmonics of the output frequency. Limit the capacitive loading on these outputs to less than 10 pF to limit the noise impact.