ZHCSTG5 October 2023 ADC12QJ1600-SEP
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
DC ACCURACY | |||||||
Resolution | Resolution with no missing codes | 12 | Bits | ||||
DNL | Differential nonlinearity | Maximum positive excursion from ideal step size | 0.2 | LSB | |||
Maximum negative excursion from ideal step size | –0.19 | ||||||
INL | Integral nonlinearity | Maximum positive excursion from ideal transfer function | 1.95 | LSB | |||
Maximum negative excursion from ideal transfer function | –1.5 | ||||||
ANALOG INPUTS (INA+, INA–, INB+, INB–) | |||||||
VOFF | Offset error | CAL_OS = 0 | ±0.6 | mV | |||
CAL_OS = 1 | ±0.6 | mV | |||||
VOFF_ADJ | Input offset voltage adjustment range | Available offset correction range (see OFSx or OFSxCh registers) | ±33 | mV | |||
VOFF_DRIFT | Offset drift | Foreground calibration at nominal temperature only, CAL_OS = 1 | -1.2 | µV/°C | |||
Foreground calibration at each temperature, CAL_OS = 1 | 0.25 | ||||||
VFS | Analog differential input full-scale range | Default full-scale voltage (FS_RANGE = 0xA000), measured at DC | 750 | 800 | 850 | mVPP | |
Maximum full-scale voltage (FS_RANGE = 0xFFFF), measured at DC | 980 | 1040 | |||||
Minimum full-scale voltage (FS_RANGE = 0x2000), measured at DC | 480 | 500 | |||||
VFS_DRIFT | Analog differential input full-scale range drift | Default FS_RANGE setting, foreground calibration at nominal temperature only, inputs driven by a 50-Ω source, includes effect of RIN drift | –0.0015 | %/°C | |||
Default FS_RANGE setting, foreground calibration at each temperature, inputs driven by a 50-Ω source, includes effect of RIN drift | -.000018 | ||||||
VFS_MATCH | Analog differential input full-scale range matching | Matching between any two channels (e.g. INA± and INB±), default full-scale voltage, measured at DC | 1% | ||||
RIN | Differential input resistance | Center of differential resistance is terminated to VCM, measured at TA = 25°C | 92 | 100 | 108 | Ω | |
RIN_TEMPCO | Input termination linear temperature coefficient | 38 | mΩ/°C | ||||
CIN | Single-ended input capacitance | Measured at DC | 0.6 | pF | |||
TEMPERATURE DIODE CHARACTERISTICS (TDIODE+, TDIODE–) | |||||||
ΔVBE | Temperature diode voltage slope | Forced forward current of 100 µA. Offset voltage (approximately 0.792 V at 0°C) varies with process and must be measured for each part. Offset measurement must be done with the device unpowered or with the PD pin asserted to minimize device self-heating. | –1.6 | mV/°C | |||
BAND-GAP VOLTAGE OUTPUT (BG) | |||||||
VBG | Internal band-gap reference and VCM reference output voltage | IL ≤ 100 µA | 1.1 | V | |||
VBG_DRIFT | VBG output temperature drift | IL ≤ 100 µA | –117 | µV/°C | |||
DIFFERENTIAL CLOCK AND TIMESTAMP INPUTS (CLK+, CLK–, SYSREF+, SYSREF–, TMSTP+, TMSTP–) | |||||||
ZT | Internal termination | Differential termination with DEVCLK_LVPECL_EN = 0, SYSREF_LVPECL_EN = 0, and TMSTP_LVPECL_EN = 0 | 100 | Ω | |||
Single-ended termination to GND (per pin) with DEVCLK_LVPECL_EN = 0, SYSREF_LVPECL_EN = 0, and TMSTP_LVPECL_EN = 0 | 50 | ||||||
VCM | Input common-mode voltage, self-biased | Self-biasing common-mode voltage for CLK± when AC-coupled (DEVCLK_LVPECL_EN must be set to 0) | 0.3 | V | |||
Self-biasing common-mode voltage for SYSREF± when AC-coupled (SYSREF_LVPECL_EN must be set to 0) and with receiver enabled (SYSREF_RECV_EN = 1) | 0.3 | ||||||
Self-biasing common-mode voltage for SYSREF± when AC-coupled (SYSREF_LVPECL_EN must be set to 0) and with receiver disabled (SYSREF_RECV_EN = 0) | VA11 | ||||||
CL_DIFF | Differential input capacitance | Between positive and negative differential input pins | 0.1 | pF | |||
CL_SE | Single-ended input capacitance | Each input to ground | 0.5 | pF | |||
CLOCK AND TRIGGER OUTPUTS (PLLREFO+, PLLREFO–, TRIGOUT+, TRIGOUT–) | |||||||
VDIFF | Differential output voltage, peak-to-peak, DC measurement | 100-Ω load | 400 | 720 | 900 | mVPP-DIFF | |
VCM(PLLREFO) | PLLREFO± output common-mode voltage | 1.31(1) | V | ||||
VCM(TRIGOUT) | TRIGOUT± output common-mode voltage, tracks with VTRIG | VTRIG = 1.9 | 1.31(2) | V | |||
VTRIG = 1.1 | 0.5(2) | ||||||
ZDIFF | Differential output impedance | Measured at DC | 300 | Ω | |||
SERDES OUTPUTS (D[7:0]+, D[7:0]–) | |||||||
VOD | Differential output voltage, peak-to-peak | 100-Ω load | 600 | mVPP-DIFF | |||
VCM | Output common-mode voltage | AC coupled | 0.54 | V | |||
ZDIFF | Differential output impedance | 100 | Ω | ||||
CMOS INTERFACE (SCLK, SDI, SDO, SCS, PD, CALSTAT, CALTRIG, CLKCFG0, CLKCFG1, PLL_EN, PLLREF_SE, ORA, ORB, ORC, ORD, SYNCSE) | |||||||
VIH | High-level input voltage | 0.7 | V | ||||
VIL | Low-level input voltage | 0.45 | V | ||||
IIH | High-level input current | 40 | µA | ||||
IIL | Low-level input current | –40 | µA | ||||
CI | Input capacitance | 2 | pF | ||||
VOH | High-level output voltage | ILOAD = –400 µA | 1.65 | V | |||
VOL | Low-level output voltage | ILOAD = 400 µA | 150 | mV |