ZHCSPP4A june   2022  – july 2023 ADC12QJ1600-SP

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 说明（续）
  6. 5 Revision History
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: DC Specifications
    6. 7.6  Electrical Characteristics: Power Consumption
    7. 7.7  Electrical Characteristics: AC Specifications
    8. 7.8  Switching Characteristics
    9. 7.9  Timing Requirements
    10. 7.10 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
        1. 8.3.1.1 Analog Input Protection
        2. 8.3.1.2 Full-Scale Voltage (VFS) Adjustment
        3. 8.3.1.3 Analog Input Offset Adjust
        4. 8.3.1.4 ADC Core
          1. 8.3.1.4.1 ADC Theory of Operation
          2. 8.3.1.4.2 ADC Core Calibration
          3. 8.3.1.4.3 Analog Reference Voltage
          4. 8.3.1.4.4 ADC Over-range Detection
          5. 8.3.1.4.5 Code Error Rate (CER)
      2. 8.3.2 Temperature Monitoring Diode
      3. 8.3.3 Timestamp
      4. 8.3.4 Clocking
        1. 8.3.4.1 Converter PLL (C-PLL) for Sampling Clock Generation
        2. 8.3.4.2 LVDS Clock Outputs (PLLREFO±, TRIGOUT±)
        3. 8.3.4.3 Optional CMOS Clock Outputs (ORC, ORD)
        4. 8.3.4.4 SYSREF for JESD204C Subclass-1 Deterministic Latency
          1. 8.3.4.4.1 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          2. 8.3.4.4.2 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
      5. 8.3.5 JESD204C Interface
        1. 8.3.5.1  Transport Layer
        2. 8.3.5.2  Scrambler
        3. 8.3.5.3  Link Layer
        4. 8.3.5.4  8B or 10B Link Layer
          1. 8.3.5.4.1 Data Encoding (8B or 10B)
          2. 8.3.5.4.2 Multiiframes and the Local Multiframe Clock (LMFC)
          3. 8.3.5.4.3 Code Group Synchronization (CGS)
          4. 8.3.5.4.4 Initial Lane Alignment Sequence (ILAS)
          5. 8.3.5.4.5 Frame and Multiframe Monitoring
        5. 8.3.5.5  64B or 66B Link Layer
          1. 8.3.5.5.1 64B or 66B Encoding
          2. 8.3.5.5.2 Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)
            1. 8.3.5.5.2.1 Block, Multiblock and Extended Multiblock Alignment using Sync Header
              1. 8.3.5.5.2.1.1 Cyclic Redundancy Check (CRC) Mode
              2. 8.3.5.5.2.1.2 Forward Error Correction (FEC) Mode
          3. 8.3.5.5.3 Initial Lane Alignment
          4. 8.3.5.5.4 Block, Multiblock and Extended Multiblock Alignment Monitoring
        6. 8.3.5.6  Physical Layer
          1. 8.3.5.6.1 SerDes Pre-Emphasis
        7. 8.3.5.7  JESD204C Enable
        8. 8.3.5.8  Multi-Device Synchronization and Deterministic Latency
        9. 8.3.5.9  Operation in Subclass 0 Systems
        10. 8.3.5.10 Alarm Monitoring
          1. 8.3.5.10.1 Clock Upset Detection
          2. 8.3.5.10.2 FIFO Upset Detection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Low Power Mode and High Performance Mode
      2. 8.4.2 JESD204C Modes
        1. 8.4.2.1 JESD204C Transport Layer Data Formats
        2. 8.4.2.2 64B or 66B Sync Header Stream Configuration
        3. 8.4.2.3 Redundant Data Mode (Alternate Lanes)
      3. 8.4.3 Power-Down Modes
      4. 8.4.4 Test Modes
        1. 8.4.4.1 Serializer Test-Mode Details
        2. 8.4.4.2 PRBS Test Modes
        3. 8.4.4.3 Clock Pattern Mode
        4. 8.4.4.4 Ramp Test Mode
        5. 8.4.4.5 Short and Long Transport Test Mode
          1. 8.4.4.5.1 Short Transport Test Pattern
        6. 8.4.4.6 D21.5 Test Mode
        7. 8.4.4.7 K28.5 Test Mode
        8. 8.4.4.8 Repeated ILA Test Mode
        9. 8.4.4.9 Modified RPAT Test Mode
      5. 8.4.5 Calibration Modes and Trimming
        1. 8.4.5.1 Foreground Calibration Mode
        2. 8.4.5.2 Background Calibration Mode
        3. 8.4.5.3 Low-Power Background Calibration (LPBG) Mode
      6. 8.4.6 Offset Calibration
      7. 8.4.7 Trimming
    5. 8.5 Programming
      1. 8.5.1 Using the Serial Interface
      2. 8.5.2 SCS
      3. 8.5.3 SCLK
      4. 8.5.4 SDI
      5. 8.5.5 SDO
      6. 8.5.6 Streaming Mode
      7. 8.5.7 SPI_Register_Map Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Light Detection and Ranging (LiDAR) Digitizer
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Analog Front-End Requirements
          2. 9.2.1.2.2 Calculating Clock and SerDes Frequencies
        3. 9.2.1.3 Application Curves
    3. 9.3 Initialization Set Up
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Power Sequencing
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
    2. 10.2 接收文档更新通知
    3. 10.3 支持资源
    4. 10.4 Trademarks
    5. 10.5 静电放电警告
    6. 10.6 术语表
  12. 11Mechanical, Packaging, and Orderable Information

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请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • ALR|144
散热焊盘机械数据 (封装 | 引脚)
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8.5.7 SPI_Register_Map Registers

Table 8-53 lists the SPI_Register_Map registers. All register offset addresses not listed in Table 8-53 should be considered as reserved locations and the register contents should not be modified.

Table 8-53 SPI_REGISTER_MAP Registers
Address Acronym Register Name Section
0x0 CONFIG_A Configuration A (default: 0x30) Go
0x2 DEVICE_CONFIG Device Configuration (default: 0x00) Go
0xC VENDOR_ID Vendor Identification (Default = 0x0451) Go
0x10 USR0 User SPI Configuration (Default: 0x00) Go
0x29 CLK_CTRL0 Clock Control 0 (default: 0x80) Go
0x2A CLK_CTRL1 Clock Control 1 (default: 0x00) Go
0x2B CLK_CTRL2 Clock Control 2 (default: 0x10) Go
0x2C SYSREF_POS SYSREF Capture Position (read-only status) Go
0x30 FS_RANGE FS_RANGE (default: 0xA000) Go
0x37 LOW_POWER1 Low Power Mode 1 (default: 0x4B) Go
0x3B TMSTP_CTRL TIMESTAMP (TMSTP) Control (default: 0x00) Go
0x3C PLLREFO_CTRL PLL Reference Output Control (default: 0x01) Go
0x3D CPLL_FBDIV1 C-PLL Feedback Divider V and P (default: 0x00) Go
0x3E CPLL_FBDIV2 C-PLL Feedback Divider N (default: 0x20) Go
0x3F CPLL_VCOCTRL1 C-PLL Feedback Divider N (default: 0x4F) Go
0x48 SER_PE Serializer Pre-Emphasis Control (default: 0x00) Go
0x57 TRIGOUT_CTRL TRIGOUT Output Control (default: 0x00) Go
0x58 CPLL_OVR C-PLL Pin Override (default: 0x00) Go
0x59 VCO_FREQ_TRIM C-PLL VCO Frequency Trim (default: undefined) Go
0x5C CPLL_RESET C-PLL / VCO Calibration Reset (default: 0x00) Go
0x5D VCO_CAL_CTRL VCO Calibration Control (default: 0x40) Go
0x5E VCO_CAL_STATUS VCO Calibration Status (read-only) (default: undefined) Go
0x61 CAL_EN Calibration Enable (Default: 0x01) Go
0x62 CAL_CFG0 Calibration Configuration 0 (Default: 0x01) Go
0x65 CAL_CFG1 Calibration Configuration 1 (Default: 0x01) Go
0x68 CAL_AVG Calibration Averaging (default: 0x61) Go
0x6A CAL_STATUS Calibration Status (default: undefined) (read-only) Go
0x6B CAL_PIN_CFG Calibration Pin Configuration (default: 0x00) Go
0x6C CAL_SOFT_TRIG Calibration Software Trigger (default: 0x01) Go
0x6E CAL_LP Low-Power Background Calibration (default: 0x88) Go
0x7A GAIN_TRIM Gain DAC Trim (default from Fuse ROM) Go
0x7C BG_TRIM Band-Gap Trim (default from Fuse ROM) Go
0x7E RTRIM_A Resistor Trim for INA (default from Fuse ROM) Go
0x7F RTRIM_B Resistor Trim for INB (default from Fuse ROM) Go
0x80 RTRIM_C Resistor Trim for INC (default from Fuse ROM) Go
0x81 RTRIM_D Resistor Trim for IND (default from Fuse ROM) Go
0x9A ADC_SRC_DLY ADC Source Delay for Calibration Section 8.5.7.37
0x9B MUX_SEL_DLY MUX selection Delay for Calibration Section 8.5.7.38
0x9D ADC_DITH ADC Dither Control (default from Fuse ROM) Go
0x160 LSB_CTRL LSB Control Bit Output (default: 0x00) Go
0x200 JESD_EN JESD204C Subsystem Enable (default: 0x01) Go
0x201 JMODE JESD204C Mode (default: 0x00) Go
0x202 KM1 JESD204C K Parameter (minus 1) (default: 0x1F) Go
0x203 JSYNC_N JESD204C Manual Sync Request (default: 0x01) Go
0x204 JCTRL JESD204C Control (default: 0x03) Go
0x205 JTEST JESD204C Test Control (default: 0x00) Go
0x206 DID JESD204C DID Parameter (default: 0x00) Go
0x207 FCHAR JESD204C Frame Character (default: 0x00) Go
0x208 JESD_STATUS JESD204C / System Status Register Go
0x209 CH_EN JESD204C Channel Enable (default: 0x03) Go
0x20F SHMODE JESD204C Sync Word Mode (default: 0x00) Go
0x210 SYNC_THRESH JESD204C SYNC~ Threshold (default: 0x03) Go
0x211 OVR_TH Over-range Threshold (default: 0xF2) Go
0x213 OVR_CFG Over-range Enable / Hold Off (default: 0x07) Go
0x270 INIT_STATUS Initialization Status (read-only) Go
0x29A LOW_POWER2 Low Power Mode 2 (default: 0x0F) Go
0x29B LOW_POWER3 Low Power Mode 3 (default: 0x04) Go
0x29C LOW_POWER4 Low Power Mode 4 (default: 0x1B) Go
0x2C0 ALARM Alarm Interrupt (read-only) Go
0x2C1 ALM_STATUS Alarm Status (default: 0x3F, write to clear) Go
0x2C2 ALM_MASK Alarm Mask Register (default: 0x3F) Go
0x2C4 FIFO_LANE_ALM FIFO Overflow/Underflow Alarm (default: 0xFF) Go
0x330 OFS0 Offset Adjustment for ADC0 (default from Fuse ROM) Go
0x332 OFS1 Offset Adjustment for ADC1 (default from Fuse ROM) Go
0x334 OFS2A Offset Adjustment for ADC2 (INA±) (default from Fuse ROM) Go
0x336 OFS2B Offset Adjustment for ADC2 (INB±) (default from Fuse ROM) Go
0x338 OFS3C Offset Adjustment for ADC3 (INC±) (default from Fuse ROM) Go
0x33A OFS3D Offset Adjustment for ADC3 (IND±) (default from Fuse ROM) Go
0x33C OFS4 Offset Adjustment for ADC4 (default from Fuse ROM) Go
0x33E OFS5 Offset Adjustment for ADC5 (default from Fuse ROM) Go
0x360 GAIN0 Fine Gain Adjust for ADC0 (default from Fuse ROM) Go
0x361 GAIN1 Fine Gain Adjust for ADC1 (default from Fuse ROM) Go
0x362 GAIN2A Fine Gain Adjust for ADC2 (INA±) (default from Fuse ROM) Go
0x363 GAIN2B Fine Gain Adjust for ADC2 (INB±) (default from Fuse ROM) Go
0x364 GAIN3C Fine Gain Adjust for ADC3 (INC±) (default from Fuse ROM) Go
0x365 GAIN3D Fine Gain Adjust for ADC3 (IND±) (default from Fuse ROM) Go
0x366 GAIN4 Fine Gain Adjust for ADC4 (default from Fuse ROM) Go
0x367 GAIN5 Fine Gain Adjust for ADC5 (default from Fuse ROM) Go

Complex bit access types are encoded to fit into small table cells. Table 8-54 shows the codes that are used for access types in this section.

Table 8-54 SPI_Register_Map Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value
Register Array Variables
i,j,k,l,m,nWhen these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
yWhen this variable is used in a register name, an offset, or an address it refers to the value of a register array.

8.5.7.1 CONFIG_A Register (Address = 0x0) [reset = 0x30]

CONFIG_A is shown in Figure 8-18 and described in Table 8-55.

Return to the Summary Table.

Configuration A (default: 0x30)

Figure 8-18 CONFIG_A Register
76543210
SOFT_RESETRESERVEDASCENDSDO_ACTIVERESERVED
R/W-0x0R/W-0x0R/W-0x1R-0x1R/W-0x0
Table 8-55 CONFIG_A Register Field Descriptions
BitFieldTypeResetDescription
7SOFT_RESETR/W0x0Setting this bit causes a full reset of the chip and all SPI registers (including CONFIG_A). This bit is self-clearing. After writing this bit, the part may take up to 750ns to reset. During this time, do not perform any SPI transactions.
6RESERVEDR/W0x0Must write default value.
5ASCENDR/W0x10 : Address is decremented during streaming reads/writes
1 : Address is incremented during streaming reads/writes (default)
4SDO_ACTIVER0x1Always returns 1. Always use SDO for SPI reads.
No SDIO mode supported.
3:0RESERVEDR/W0x0

8.5.7.2 DEVICE_CONFIG Register (Address = 0x2) [reset = 0x00]

DEVICE_CONFIG is shown in Figure 8-19 and described in Table 8-56.

Return to the Summary Table.

Device Configuration (default: 0x00)

Figure 8-19 DEVICE_CONFIG Register
76543210
RESERVEDMODE
R/W-0x0R/W-0x0
Table 8-56 DEVICE_CONFIG Register Field Descriptions
BitFieldTypeResetDescription
7:2RESERVEDR/W0x0Must write default value.
1:0MODER/W0x00 : Normal operation (default)
1 : Reserved
2 : Reserved
3 : Power down (full device)

8.5.7.3 VENDOR_ID Register (Address = 0xC) [reset = 0x0]

VENDOR_ID is shown in Figure 8-20 and described in Table 8-57.

Return to the Summary Table.

Vendor Identification (Default = 0x0451)

Figure 8-20 VENDOR_ID Register
15141312111098
VENDOR_ID
R-0x0
76543210
VENDOR_ID
R-0x0
Table 8-57 VENDOR_ID Register Field Descriptions
BitFieldTypeResetDescription
15:0VENDOR_IDR0x0Always returns 0x0451 (Vendor ID for Texas Instruments)

8.5.7.4 USR0 Register (Address = 0x10) [reset = 0x00]

USR0 is shown in Figure 8-21 and described in Table 8-58.

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User SPI Configuration (Default: 0x00)

Figure 8-21 USR0 Register
76543210
RESERVEDADDR_HOLD
R/W-0x0R/W-0x0
Table 8-58 USR0 Register Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR/W0x0Must write default value.
0ADDR_HOLDR/W0x00 : Use ASCEND register to select address ascend/descend mode (default)
1 : Address stays constant throughout streaming operation; useful for reading and writing calibration vector information at the CAL_DATA register

8.5.7.5 CLK_CTRL0 Register (Address = 0x29) [reset = 0x80]

CLK_CTRL0 is shown in Figure 8-22 and described in Table 8-59.

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Clock Control 0 (default: 0x80)

Figure 8-22 CLK_CTRL0 Register
76543210
RESERVEDSYSREF_PROC_ENSYSREF_RECV_ENSYSREF_ZOOMSYSREF_SEL
R/W-0x1R/W-0x0R/W-0x0R/W-0x0R/W-0x0
Table 8-59 CLK_CTRL0 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0x1Must write default value.
6SYSREF_PROC_ENR/W0x0This bit enables the SYSREF processor, which allows the device to process SYSREF events (default: disabled). SYSREF_RECV_EN must be set before setting SYSREF_PROC_EN.
5SYSREF_RECV_ENR/W0x0Set this bit to enable the SYSREF receiver circuit (default: disabled)
4SYSREF_ZOOMR/W0x0Set this bit to zoom in the SYSREF windowing status and delays (impacts SYSERF_POS and SYSREF_SEL). When set, the delays used in the SYSREF windowing feature (reported in the SYSREF_POS register) become smaller. Use SYSREF_ZOOM for high clock rates, specifically when multiple SYSREF valid windows are encountered in the SYSREF_POS register; see the SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing) section.
3:0SYSREF_SELR/W0x0Set this field to select which SYSREF delay to use. Set this field based on the results returned by SYSREF_POS; see the SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing) section.

8.5.7.6 CLK_CTRL1 Register (Address = 0x2A) [reset = 0x00]

CLK_CTRL1 is shown in Figure 8-23 and described in Table 8-60.

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Clock Control 1 (default: 0x00)

Figure 8-23 CLK_CTRL1 Register
76543210
RESERVEDDEVCLK_LVPECL_ENSYSREF_LVPECL_ENSYSREF_INVERTED
R/W-0x0R/W-0x0R/W-0x0R/W-0x0
Table 8-60 CLK_CTRL1 Register Field Descriptions
BitFieldTypeResetDescription
7:3RESERVEDR/W0x0Must write default value.
2DEVCLK_LVPECL_ENR/W0x0Activate low voltage PECL mode for DEVCLK. The internal termination for each input pin (CLK+ and CLK–) becomes a 50-Ω resistor to ground. There is no input common-mode self-biasing for CLK± when DEVCLK_LVPECL_EN is set to 1.
1SYSREF_LVPECL_ENR/W0x0Activate low voltage PECL mode for SYSREF. The internal termination for each input pin (SYSREF+ and SYSREF–) becomes a 50-Ω resistor to ground. There is no input common-mode self-biasing for SYSREF± when SYSREF_LVPECL_EN is set to 1.
0SYSREF_INVERTEDR/W0x0This bit inverts the SYSREF signal used for alignment.

8.5.7.7 CLK_CTRL2 Register (Address = 0x2B) [reset = 0x10]

CLK_CTRL2 is shown in Figure 8-24 and described in Table 8-61.

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Clock Control 1 (default: 0x10)

Figure 8-24 CLK_CTRL2 Register
76543210
RESERVEDVA11Q_NOISESUPPR_ENRESERVEDVCLK11_NOISESUPPR_EN
R/W-0x1R/W-0x0R/W-0x0R/W-0x0
Table 8-61 CLK_CTRL2 Register Field Descriptions
BitFieldTypeResetDescription
7:3RESERVEDR/W0x0Must write default value.
2VA11Q_NOISESUPPR_ENR/W0x0When set, noise on VA11Q is suppressed while drawing ~ 20mA of current. This will reduce sampling jitter and reduce the reference clock spur in C-PLL modes and SYSREF spurs.
1RESERVEDR/W0x0Must write default value.
0VCLK11_NOISESUPPR_ENR/W0x0When set, noise on VCLK11 is suppressed while drawing ~ 20mA of current. This will reduce sampling jitter and reduce the reference clock spur in C-PLL modes and SYSREF spurs.

8.5.7.8 SYSREF_POS Register (Address = 0x2C) [reset = 0x0]

SYSREF_POS is shown in Figure 8-25 and described in Table 8-62.

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SYSREF Capture Position (read-only status)

Figure 8-25 SYSREF_POS Register
2322212019181716
SYSREF_POS
R-0x0
15141312111098
SYSREF_POS
R-0x0
76543210
SYSREF_POS
R-0x0
Table 8-62 SYSREF_POS Register Field Descriptions
BitFieldTypeResetDescription
23:0SYSREF_POSR0x0Returns a 24-bit status value that indicates the position of the SYSREF edge with respect to CLK±. Use this to program SYSREF_SEL.

8.5.7.9 FS_RANGE Register (Address = 0x30) [reset = 0xA000]

FS_RANGE is shown in Figure 8-26 and described in Table 8-63.

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FS_RANGE (default: 0xA000)

Figure 8-26 FS_RANGE Register
15141312111098
FS_RANGE
R/W-0xA000
76543210
FS_RANGE
R/W-0xA000
Table 8-63 FS_RANGE Register Field Descriptions
BitFieldTypeResetDescription
15:0FS_RANGER/W0xA000These bits enable adjustment of the analog full-scale range for all channels.
0x0000: Settings below 0x2000 result in degraded performance
0x2000: 500 mVPP - Recommended minimum setting
0xA000: 800 mVPP (default)
0xFFFF: 1000 mVPP - Maximum setting, highest SNR

8.5.7.10 LOW_POWER1 Register (Address = 0x37) [reset = 0x4B]

LOW_POWER1 is shown in Figure 8-27 and described in Table 8-64.

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Low Power Mode 1 (default: 0x4B)

Figure 8-27 LOW_POWER1 Register
76543210
LOW_POW_MODE1
R/W-0x4B
Table 8-64 LOW_POWER1 Register Field Descriptions
BitFieldTypeResetDescription
7:0LOW_POW_MODE1R/W0x4BSet this register along with LOW_POWER2, LOW_POWER3 and LOW_POWER4 to enable Low Power Mode. All registers must be set together. Calibration must be performed after changing the operating mode:

0x46 : Low Power Mode (only valid when sampling rate is less than or equal to 1 GSPS)
0x4B : High Performance Mode (default)
All other values are RESERVED

Note: Must set CAL_EN to 0 and JESD_EN to 0 before changing this register.

8.5.7.11 TMSTP_CTRL Register (Address = 0x3B) [reset = 0x00]

TMSTP_CTRL is shown in Figure 8-28 and described in Table 8-65.

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TIMESTAMP (TMSTP) Control (default: 0x00)

Figure 8-28 TMSTP_CTRL Register
76543210
RESERVEDTMSTP_LVPECL_ENTMSTP_RECV_EN
R/W-0x0R/W-0x0R/W-0x0
Table 8-65 TMSTP_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7:2RESERVEDR/W0x0Must write default value.
1TMSTP_LVPECL_ENR/W0x0When set, activates the low voltage PECL mode for the differential TMSTP± input. The internal termination for each input pin (TMSTP+ and TMSTP–) becomes a 50-Ω resistor to ground. There is no input common-mode self-biasing for TMSTP± when TMSTP_LVPECL_EN is set to 1.
0TMSTP_RECV_ENR/W0x0Enables the differential differential TMSTP± input.

8.5.7.12 PLLREFO_CTRL Register (Address = 0x3C) [reset = 0x01]

PLLREFO_CTRL is shown in Figure 8-29 and described in Table 8-66.

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PLL Reference Output Control (default: 0x01)

Figure 8-29 PLLREFO_CTRL Register
76543210
RESERVEDPLLREFO_EN
R/W-0x0R/W-0x1
Table 8-66 PLLREFO_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR/W0x0Must write default value.
0PLLREFO_ENR/W0x1When set the reference clock output (PLLREFO±) is enabled whenever the PLL is enabled (PLL_EN=1). This bit defaults to 1 to cause PLLREFO± to enable automatically without SPI writes since PLLREFO± may be used to derive the SPI clock.

8.5.7.13 CPLL_FBDIV1 Register (Address = 0x3D) [reset = 0x00]

CPLL_FBDIV1 is shown in Figure 8-30 and described in Table 8-67.

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C-PLL Feedback Divider V and P (default: 0x00)

Figure 8-30 CPLL_FBDIV1 Register
76543210
RESERVEDPLL_P_DIVPLL_V_DIV
R/W-0x0R/W-0x0R/W-0x0
Table 8-67 CPLL_FBDIV1 Register Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR/W0x0Must write default value.
3:2PLL_P_DIVR/W0x0Controls the second feedback divider of C-PLL. The output of this divider is the sampling clock. Set CPLL_RESET=1 before changing PLL_P_DIV.
0 : divide-by-1 (default)
1 : divide-by-2
2 : divide-by-4
3 : RESERVED
1:0PLL_V_DIVR/W0x0Controls the first feedback divider of C-PLL. The output of this divider feeds the P divider. Set CPLL_RESET=1 before changing PLL_V_DIV.
0 : divide-by-5 (default)
1 : divide-by-4
2 : divide-by-3
3 : RESERVED

8.5.7.14 CPLL_FBDIV2 Register (Address = 0x3E) [reset = 0x20]

CPLL_FBDIV2 is shown in Figure 8-31 and described in Table 8-68.

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C-PLL Feedback Divider N (default: 0x20)

Figure 8-31 CPLL_FBDIV2 Register
76543210
RESERVEDPLL_N_DIV
R/W-0x0R/W-0x20
Table 8-68 CPLL_FBDIV2 Register Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR/W0x0Must write default value.
5:0PLL_N_DIVR/W0x20Controls the third feedback divider of C-PLL (default is divide-by-32). This divider divides the sampling clock to generate the PFD feedback clock. The value of PLL_N_DIV is the divider value. Values from 1 to 63 are supported. Set CPLL_RESET=1 before changing PLL_N_DIV.

8.5.7.15 CPLL_VCOCTRL1 Register (Address = 0x3F) [reset = 0x4F, recommended 0x4A]

CPLL_VCOCTRL1 is shown in Figure 8-32 and described in Table 8-69.

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C-PLL Feedback Divider N (default: 0x4F)

Figure 8-32 CPLL_VCOCTRL1 Register
76543210
RESERVEDVCO_BIAS
R/W-0x0R/W-0x4F
Table 8-69 CPLL_VCOCTRL1 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0x0Must write default value.
6:0VCO_BIASR/W0x4FSets the bias levels for the C-PLL VCO. Write 0x4A to this field when using the C-PLL. Do not use the default value of 0x4F.

8.5.7.16 SER_PE Register (Address = 0x48) [reset = 0x00]

SER_PE is shown in Figure 8-33 and described in Table 8-70.

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Serializer Pre-Emphasis Control (default: 0x00)

Figure 8-33 SER_PE Register
76543210
RESERVEDSER_PE
R/W-0x0R/W-0x0
Table 8-70 SER_PE Register Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR/W0x0Must write default value.
3:0SER_PER/W0x0Sets the pre-emphasis for the SerDes output lanes. Pre-emphasis can be used to compensate for the high-frequency loss of the PCB trace. This is a global setting that affects all lanes (D[7:0]±).

8.5.7.17 TRIGOUT_CTRL Register (Address = 0x57) [reset = 0x00]

TRIGOUT_CTRL is shown in Figure 8-34 and described in Table 8-71.

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TRIGOUT Output Control (default: 0x00)

Figure 8-34 TRIGOUT_CTRL Register
76543210
TRIGOUT_ENRESERVEDTRIGOUT
R/W-0x0R/W-0x0R/W-0x0
Table 8-71 TRIGOUT_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7TRIGOUT_ENR/W0x00 : TRIGOUT± output buffer/divider is disabled.
1 : TRIGOUT± output buffer/divider is enabled.
The RXCLK output can be used to provide a reference clock for the JESD204C receiver. Use the TRIGOUT_MODE field to adjust the output mode.
6:3RESERVEDR/W0x0Must write default value.
2:0TRIGOUTR/W0x0Set the mode for the TRIGOUT± output.
0 : 16 UI clock (RX_DIV = 16)
1 : 32 UI clock (RX_DIV = 32)
2 : 64 UI clock (RX_DIV = 64)
3 : Resampled timestamp from TMSTP±
4-7 : RESERVED

Note 1: Only change TRIGOUT_MODE when TRIGOUT_EN=0.
Note 2: When TRIGOUT_MODE is 2 or less, TRIGOUT± is derived from the SerDes block. As a result, the TRIGOUT± output is briefly disrupted any time the serializer is re-initialized.

8.5.7.18 CPLL_OVR Register (Address = 0x58) [reset = 0x00]

CPLL_OVR is shown in Figure 8-35 and described in Table 8-72.

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C-PLL Pin Override (default: 0x00)

Figure 8-35 CPLL_OVR Register
76543210
CPLL_OVR_ENRESERVEDDIVREF_D_MODEDIVREF_C_MODECPLLREF_SE_OVR_VALUECPLL_EN_OVR_VALUE
R/W-0x0R/W-0x0R/W-0x0R/W-0x0R/W-0x0R/W-0x0
Table 8-72 CPLL_OVR Register Field Descriptions
BitFieldTypeResetDescription
7CPLL_OVR_ENR/W0x0Set this bit to ignore the C-PLL configuration pins and use SPI registers instead.
0 : Pin Mode : The C-PLL is controlled by chip pins (PLL_EN, PLLREF_SE, CLKCFG0, CLKCFG1)
1 : SPI Mode : The C-PLL is controlled by SPI registers (CPLLREF_SE_OVR_VALUE, CPLL_EN_OVR_VALUE, DIVREF_C_MODE, DIVREF_D_MODE)
6RESERVEDR/W0x0Must write default value.
5:4DIVREF_D_MODER/W0x0When CPLL_OVR_EN=1, this field sets the ORD output function. When CPLL_OVR_EN=0, this field has no effect (CLKCFG0 and CLKCFG1 controls ORD functionality).
0 : Divided reference output is disabled.
1 : Output C-PLL reference clock divided by 1 on ORD.
2 : Output C-PLL reference clock divided by 2 on ORD.
3 : Output C-PLL reference clock divided by 4 on ORD.
**Important Note: ORD cannot produce a clock unless ORC is also producing a clock).
3:2DIVREF_C_MODER/W0x0When CPLL_OVR_EN=1, this field sets the ORC output function. When CPLL_OVR_EN=0, this field has no effect (CLKCFG0 and CLKCFG1 controls ORC functionality).
0 : Divided reference output is disabled.
1 : Output C-PLL reference clock divided by 1 on ORC.
2 : Output C-PLL reference clock divided by 2 on ORC.
3 : Output C-PLL reference clock divided by 4 on ORC.
1CPLLREF_SE_OVR_VALUER/W0x0When CPLL_OVR_EN=1, this bit enables the single-ended C-PLL reference clock input (SE_CLK) when set to 1 instead of the PLLREF_SE pin.
0CPLL_EN_OVR_VALUER/W0x0When CPLL_OVR_EN=1, this bit enables the C-PLL when set to 1 instead of the PLL_EN pin.

8.5.7.19 VCO_FREQ_TRIM Register (Address = 0x59) [reset = 0x0]

VCO_FREQ_TRIM is shown in Figure 8-36 and described in Table 8-73.

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C-PLL VCO Frequency Trim (default: undefined)

Figure 8-36 VCO_FREQ_TRIM Register
76543210
RESERVEDVCO_FREQ_TRIM
R/W-0x0R/W-0x0
Table 8-73 VCO_FREQ_TRIM Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0x0Must write default value.
6:0VCO_FREQ_TRIMR/W0x0Trims C-PLL VCO frequency. This field can be automatically set by the VCO calibration routine (see VCO_CAL_EN). After VCO calibration has been run the value can be read from this field and reprogrammed after future power-up cycles.

If VCO calibration is running (VCO_CAL_EN=1 and VCO_CAL_DONE=0), you should not read or write this register since it will interfere with the calibration process.

8.5.7.20 CPLL_RESET Register (Address = 0x5C) [reset = 0x00]

CPLL_RESET is shown in Figure 8-37 and described in Table 8-74.

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C-PLL / VCO Calibration Reset (default: 0x00)

Figure 8-37 CPLL_RESET Register
76543210
RESERVEDCPLL_RESET
R/W-0x0R/W-0x0
Table 8-74 CPLL_RESET Register Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR/W0x0Must write default value.
0CPLL_RESETR/W0x0C-PLL / VCO calibration reset. Program CPLL_RESET=1 before programming the C-PLL (PLL_P_DIV, PLL_V_DIV, PLL_N_DIV, VCO_BIAS or VCO_CAL_CTRL). Program CPLL_RESET=0 after programming is completed.

8.5.7.21 VCO_CAL_CTRL Register (Address = 0x5D) [reset = 0x40]

VCO_CAL_CTRL is shown in Figure 8-38 and described in Table 8-75.

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VCO Calibration Control (default: 0x40)

Figure 8-38 VCO_CAL_CTRL Register
76543210
RESERVEDVCO_CAL_STLRESERVEDVCO_CAL_EN
R/W-0x0R/W-0x4R/W-0x0R/W-0x0
Table 8-75 VCO_CAL_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0x0Must write default value.
6:4VCO_CAL_STLR/W0x4Program this field to adjust the settling time that the VCO calibration engine gives to the C-PLL each time it changes the VCO frequency trim (VCO_FREQ_TRIM). Larger numbers result in longer settling times.
3:1RESERVEDR/W0x0Must write default value.
0VCO_CAL_ENR/W0x0Set this bit to enable the VCO calibration engine. The calibration commences once CPLL_RESET is programmed to 0. The calibration will automatically tune VCO_FREQ_TRIM to center the VCO frequency based on the reference frequency and PLL configuration.

Note: The VCO_CAL_CTRL register should only be changed when CPLL_RESET=1.

8.5.7.22 VCO_CAL_STATUS Register (Address = 0x5E) [reset = 0x0]

VCO_CAL_STATUS is shown in Figure 8-39 and described in Table 8-76.

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VCO Calibration Status (read-only) (default: undefined)

Figure 8-39 VCO_CAL_STATUS Register
76543210
RESERVEDVCO_CAL_DONE
R-0x0R-0x0
Table 8-76 VCO_CAL_STATUS Register Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR0x0
0VCO_CAL_DONER0x0This bit returns ‘1’ once the VCO calibration engine has completed calibration (or calibration was skipped because VCO_CAL_EN=0). Once the calibration is completed, you can safely read or write the VCO_FREQ_TRIM register (never write VCO_FREQ_TRIM during calibration).

8.5.7.23 CAL_EN Register (Address = 0x61) [reset = 0x01]

CAL_EN is shown in Figure 8-40 and described in Table 8-77.

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Calibration Enable (Default: 0x01)

Figure 8-40 CAL_EN Register
76543210
RESERVEDCAL_EN
R/W-0x0R/W-0x1
Table 8-77 CAL_EN Register Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR/W0x0Must write default value.
0CAL_ENR/W0x1Calibration Enable. Set high to run calibration. Set low to hold calibration in reset to program new calibration settings. Clearing CAL_EN also resets the clock dividers that clock the digital block and JESD204C interface.

Some calibration registers require clearing CAL_EN before making any changes. All registers with this requirement contain a note in their descriptions. After changing the registers, set CAL_EN to re-run calibration with the new settings. Always set CAL_EN before setting JESD_EN. Always clear JESD_EN before clearing CAL_EN.

8.5.7.24 CAL_CFG0 Register (Address = 0x62) [reset = 0x01]

CAL_CFG0 is shown in Figure 8-41 and described in Table 8-78.

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Calibration Configuration 0 (Default: 0x01)

Figure 8-41 CAL_CFG0 Register
76543210
RESERVEDCAL_BGOSCAL_OSCAL_BGCAL_FG
R/W-0x0R/W-0x0R/W-0x0R/W-0x0R/W-0x1
Table 8-78 CAL_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR/W0x0Must write default value.
3CAL_BGOSR/W0x00 : Disable background offset calibration (default)
1 : Enable background offset calibration (requires CAL_BG to be set).
2CAL_OSR/W0x00 : Disable foreground offset calibration (default)
1 : Enable foreground offset calibration (requires CAL_FG to be set).
1CAL_BGR/W0x00 : Disable background calibration (default)
1 : Enable background calibration
0CAL_FGR/W0x10 : Reset calibration values, skip foreground calibration.
1 : Reset calibration values, then run foreground calibration (default).

8.5.7.25 CAL_CFG1 Register (Address = 0x65) [reset = 0x01]

CAL_CFG1 is shown in Figure 8-42 and described in Table 8-79.

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Calibration Configuration 1 (Default: 0x01)

Figure 8-42 CAL_CFG1 Register
76543210
RESERVEDOSREFRESERVED
R/W-0x0R/W-0x0R/W-0x1
Table 8-79 CAL_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
7:3RESERVEDR/W0x0Must write default value.
2OSREFR/W0x0Defines which reference is used for offset calibration:
0 : Use mid-code as the reference (calibrate to zero-offset). The analog input signal must have no offset during offset calibration (typically true if AC-coupled).
1 : Use the spare ADC output samples as the reference (calibrates primary ADC offsets to match the spare ADC that stands in for them). The analog input signal can have an offset (e.g. DC-coupled). Only use this mode when CAL_BG=1. Setting OSREF=1 while CAL_BG=0 will produce undefined results.
1:0RESERVEDR/W0x1Must write default value.

8.5.7.26 CAL_AVG Register (Address = 0x68) [reset = 0x61]

CAL_AVG is shown in Figure 8-43 and described in Table 8-80.

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Calibration Averaging (default: 0x61)

Figure 8-43 CAL_AVG Register
76543210
RESERVEDOS_AVGRESERVEDCAL_AVG
R/W-0x0R/W-0x6R/W-0x0R/W-0x1
Table 8-80 CAL_AVG Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0x0Must write default value.
6:4OS_AVGR/W0x6Select the amount of averaging used for the offset correction routine. A larger number corresponds to more averaging.
3RESERVEDR/W0x0Must write default value.
2:0CAL_AVGR/W0x1Select the amount of averaging used for the linearity calibration routine. A larger number corresponds to more averaging.

8.5.7.27 CAL_STATUS Register (Address = 0x6A) [reset = 0x0]

CAL_STATUS is shown in Figure 8-44 and described in Table 8-81.

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Calibration Status (default: undefined) (read-only)

Figure 8-44 CAL_STATUS Register
76543210
RESERVEDCAL_STATCAL_STOPPEDFG_DONE
R-0x0R-0x0R-0x0R-0x0
Table 8-81 CAL_STATUS Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0x0
4:2CAL_STATR0x0Calibration status code
1CAL_STOPPEDR0x0This bit returns a 1 when background calibration is successfully stopped at the requested phase. This bit returns a 0 when calibration starts operating again. If background calibration is disabled, this bit is set when foreground calibration is completed or skipped.
0FG_DONER0x0This bit is high to indicate that foreground calibration has completed (or was skipped).

8.5.7.28 CAL_PIN_CFG Register (Address = 0x6B) [reset = 0x00]

CAL_PIN_CFG is shown in Figure 8-45 and described in Table 8-82.

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Calibration Pin Configuration (default: 0x00)

Figure 8-45 CAL_PIN_CFG Register
76543210
RESERVEDCAL_STATUS_SELCAL_TRIG_EN
R/W-0x0R/W-0x0R/W-0x0
Table 8-82 CAL_PIN_CFG Register Field Descriptions
BitFieldTypeResetDescription
7:3RESERVEDR/W0x0Must write default value.
2:1CAL_STATUS_SELR/W0x00 : CALSTAT output matches FG_DONE.
1 : CALSTAT output matches CAL_STOPPED.
2 : CALSTAT output matches ALARM.
3 : CALSTAT output is always low.
0CAL_TRIG_ENR/W0x0This bit selects the hardware or software trigger source.
0 : Use the CAL_SOFT_TRIG register for the calibration trigger. The CALTRIG input is disabled (ignored).
1 : Use the CALTRIG input for the calibration trigger. The CAL_SOFT_TRIG register is ignored.

8.5.7.29 CAL_SOFT_TRIG Register (Address = 0x6C) [reset = 0x01]

CAL_SOFT_TRIG is shown in Figure 8-46 and described in Table 8-83.

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Calibration Software Trigger (default: 0x01)

Figure 8-46 CAL_SOFT_TRIG Register
76543210
RESERVEDCAL_SOFT_TRIG
R/W-0x0R/W-0x1
Table 8-83 CAL_SOFT_TRIG Register Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR/W0x0Must write default value.
0CAL_SOFT_TRIGR/W0x1CAL_SOFT_TRIG is a software bit to provide the functionality of the CALTRIG input pin when there are no hardware resources to drive CALTRIG. Program CAL_TRIG_EN=0 to use CAL_SOFT_TRIG for the calibration trigger.
Note: If no calibration trigger is needed, leave CAL_TRIG_EN=0 and CAL_SOFT_TRIG=1 (trigger set high).

8.5.7.30 CAL_LP Register (Address = 0x6E) [reset = 0x88]

CAL_LP is shown in Figure 8-47 and described in Table 8-84.

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Low-Power Background Calibration (default: 0x88)

Figure 8-47 CAL_LP Register
76543210
LP_SLEEP_DLYLP_WAKE_DLYRESERVEDLP_TRIGLP_EN
R/W-0x4R/W-0x1R/W-0x0R/W-0x0R/W-0x0
Table 8-84 CAL_LP Register Field Descriptions
BitFieldTypeResetDescription
7:5LP_SLEEP_DLYR/W0x4These bits adjust how long an ADC sleeps before waking for calibration (only applies when LP_EN = 1 and LP_TRIG = 0). Values below 4 are not recommended because of limited overall power reduction benefits.
0: Sleep delay = 1,152 × tCLK
1: Sleep delay = 4,194,432 × tCLK
2: Sleep delay = 33,554,560 × tCLK
3: Sleep delay = 268,435,584‬ × tCLK
4: Sleep delay = 2,147,483,776 × tCLK (default, approximately 2.15 seconds with a 1.0-GHz clock)
5: Sleep delay = 17,179,869,312‬× tCLK
6: Sleep delay = 137,438,953,600‬ × tCLK
7: Sleep delay = 1,099,511,627,904‬ × tCLK
4:3LP_WAKE_DLYR/W0x1These bits adjust how much time is provided for settling before calibrating an ADC after the ADC wakes up (only applies when LP_EN = 1). Values lower than 1 are not recommended because there is insufficient time for the core to stabilize before calibration begins.
0: Wake delay = 1,152 × tCLK
1: Wake delay = 33,554,560 × tCLK (default, approximately 34 ms with a 1.0-GHz clock)
2: Wake delay = 268,435,584 × tCLK
3: Wake delay = 2,147,483,776 × tCLK
2RESERVEDR/W0x0Must write default value.
1LP_TRIGR/W0x00 : ADC sleep duration is set by LP_SLEEP_DLY (autonomous mode).
1 : ADCs sleep until awoken by a trigger. An ADC is awoken when the calibration trigger is low. The offline ADC is sleeping when the calibration trigger is high.
0LP_ENR/W0x00 : Disable low-power background calibration (default)
1 : Enable low-power background calibration (only applies when CAL_BG=1).

8.5.7.31 GAIN_TRIM Register (Address = 0x7A) [reset = 0x0]

GAIN_TRIM is shown in Figure 8-48 and described in Table 8-85.

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Gain DAC Trim (default from Fuse ROM)

Figure 8-48 GAIN_TRIM Register
76543210
GAIN_TRIM
R/W-0x0
Table 8-85 GAIN_TRIM Register Field Descriptions
BitFieldTypeResetDescription
7:0GAIN_TRIMR/W0x0This register trims the gain of all ADC cores. FS_RANGE should be used for full-scale range adjustment instead of GAIN_TRIM.

8.5.7.32 BG_TRIM Register (Address = 0x7C) [reset = 0x0]

BG_TRIM is shown in Figure 8-49 and described in Table 8-86.

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Band-Gap Trim (default from Fuse ROM)

Figure 8-49 BG_TRIM Register
76543210
RESERVEDBG_TRIM
R/W-0x0R/W-0x0
Table 8-86 BG_TRIM Register Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR/W0x0Must write default value.
3:0BG_TRIMR/W0x0This register enables trimming of the internal band-gap reference. After reset, the factory trimmed value can be read and adjusted as required.

8.5.7.33 RTRIM_A Register (Address = 0x7E) [reset = 0x0]

RTRIM_A is shown in Figure 8-50 and described in Table 8-87.

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Resistor Trim for INA (default from Fuse ROM)

Figure 8-50 RTRIM_A Register
76543210
RTRIM_A
R/W-0x0
Table 8-87 RTRIM_A Register Field Descriptions
BitFieldTypeResetDescription
7:0RTRIM_AR/W0x0This register controls the INA± ADC input termination trim. After reset, the factory trimmed value can be read and adjusted as required.

8.5.7.34 RTRIM_B Register (Address = 0x7F) [reset = 0x0]

RTRIM_B is shown in Figure 8-51 and described in Table 8-88.

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Resistor Trim for INB (default from Fuse ROM)

Figure 8-51 RTRIM_B Register
76543210
RTRIM_B
R/W-0x0
Table 8-88 RTRIM_B Register Field Descriptions
BitFieldTypeResetDescription
7:0RTRIM_BR/W0x0This register controls the INB± ADC input termination trim. After reset, the factory trimmed value can be read and adjusted as required.

8.5.7.35 RTRIM_C Register (Address = 0x80) [reset = 0x0]

RTRIM_C is shown in Figure 8-52 and described in Table 8-89.

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Resistor Trim for INC (default from Fuse ROM)

Figure 8-52 RTRIM_C Register
76543210
RTRIM_C
R/W-0x0
Table 8-89 RTRIM_C Register Field Descriptions
BitFieldTypeResetDescription
7:0RTRIM_CR/W0x0This register controls the INC± ADC input termination trim. After reset, the factory trimmed value can be read and adjusted as required.

8.5.7.36 RTRIM_D Register (Address = 0x81) [reset = 0x0]

RTRIM_D is shown in Figure 8-53 and described in Table 8-90.

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Resistor Trim for IND (default from Fuse ROM)

Figure 8-53 RTRIM_D Register
76543210
RTRIM_D
R/W-0x0
Table 8-90 RTRIM_D Register Field Descriptions
BitFieldTypeResetDescription
7:0RTRIM_DR/W0x0This register controls the IND± ADC input termination trim. After reset, the factory trimmed value can be read and adjusted as required.

8.5.7.37 ADC Source Control Delay (Address = 0x9A) [reset = 0x08]

ADC_SRC_DLY is shown in AC_SRC_DLY Register and described in ADC_SRC_DLY Register Field Descriptions. Only change this register while CAL_EN is 0.

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ADC Dither Control (default from Fuse ROM)

Figure 8-54 ADC_SRC_DLY Register
76543210
RESERVED
R/W-0x0R/W-0x08
Table 8-91 ADC_SRC_DLY Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR/W0x0Must write default value.
4:0ADC_SRC_DLYR/W0x08

Adjusts how long two ADCs will sample the same input at the same clock phase during background ADC swaps.

The default value is appropriate for all ADCCLK frequencies. If using a reduced ADCCLK frequency, ADC_SRC_DLY can be set to 7 to reduce the glitch duration during fast background ADC swaps, however there is a greater risk of having a large glitch amplitude.

Two ADCs will sample the same input for 4+2*ADC_SRC_DLY ADCCLK cycles.

ADC_SRC_DLY can be programmed from 0 to 31.

8.5.7.38 MUX Select Delay Register (Address = 0x9B) [reset = 0x07]

MUX_SEL_DLY is shown in MUX_SEL_DLY Register and described in MUX_SEL_DLY Register Field Descriptions.

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Figure 8-55 MUX_SEL_DLY Register
76543210
RESERVEDMUX_SEL_DLY
R/W-0x0R/W-0x07
Table 8-92 MUX_SEL_DLY Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR/W0x0Must write default value.
4:0MUX_SEL_DLYR/W0x07

Adjusts the delay added to the internal mux selection signal. This signal controls multiplexors that steer ADC core output data into the encoders. This delay only applies during background ADC swaps. This delay needs to be tuned to swap between sample streams during a small window of time when both sample streams are valid.

MUX_SEL_DLY can be programmed from 0 to 31.

8.5.7.39 ADC_DITH Register (Address = 0x9D) [reset = 0x0]

ADC_DITH is shown in Figure 8-56 and described in Table 8-93.

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ADC Dither Control (default from Fuse ROM)

Figure 8-56 ADC_DITH Register
76543210
RESERVEDADC_DITH_ERRADC_DITH_AMPADC_DITH_EN
R/W-0x0R/W-0x0R/W-0x0R/W-0x0
Table 8-93 ADC_DITH Register Field Descriptions
BitFieldTypeResetDescription
7:3RESERVEDR/W0x0Must write default value.
2ADC_DITH_ERRR/W0x0Small rounding errors may occur when subtracting the dither signal. The error can be chosen to either slightly degrade SNR or to slightly increase the DC offset and FS/2 spur. In addition, the FS/4 spur will also be increased slightly while in single channel mode.
0 : Rounding error degrades SNR
1 : Rounding error degrades DC offset, FS/2 spur and FS/4 spur
1ADC_DITH_AMPR/W0x00 : Small dither for better SNR (default)
1 : Large dither for better spurious performance
0ADC_DITH_ENR/W0x0Set this bit to enable ADC dither. Dither can improve spurious performance at the expense of slightly degraded SNR. The dither amplitude (ADC_DITH_AMP) can be used to further tradeoff SNR and spurious performance.

8.5.7.40 LSB_CTRL Register (Address = 0x160) [reset = 0x00]

LSB_CTRL is shown in Figure 8-57 and described in Table 8-94.

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LSB Control Bit Output (default: 0x00)

Figure 8-57 LSB_CTRL Register
76543210
RESERVEDTIME_STAMP_EN
R/W-0x0R/W-0x0
Table 8-94 LSB_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR/W0x0Must write default value.
0TIME_STAMP_ENR/W0x0When set, the transport layer transmits the timestamp signal on the LSB of the output samples. The latency of the timestamp signal (through the entire chip) should match the latency of the analog ADC inputs. Please also set TMSTP_RECV_EN when using TIME_STAMP_EN.

Note 1: The control bit is placed on the LSB of the JESD204C samples. In some cases, the JESD204C sample width (N) is greater than the sample width from the ADC. In these cases, the control bit does not replace the LSB of the ADC sample since it is placed at the LSB of the N-bit field).

Note 2: The control bit that is enabled by this register is never advertised in the ILA (CS is 0 in the ILA).

8.5.7.41 JESD_EN Register (Address = 0x200) [reset = 0x01]

JESD_EN is shown in Figure 8-58 and described in Table 8-95.

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JESD204C Subsystem Enable (default: 0x01)

Figure 8-58 JESD_EN Register
76543210
RESERVEDJESD_EN
R/W-0x0R/W-0x1
Table 8-95 JESD_EN Register Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR/W0x0Must write default value.
0JESD_ENR/W0x10 : Disable JESD204C interface
1 : Enable JESD204C interface

Note: Before altering other JESD204C registers, you must clear JESD_EN. When JESD_EN is 0, the block is held in reset and the serializers are powered down. The clocks are gated off to save power. The LMFC/LEMC counter is also held in reset, so SYSREF will not align the LMFC/LEMC.

Note: Always set CAL_EN before setting JESD_EN.
Note: Always clear JESD_EN before clearing CAL_EN.

8.5.7.42 JMODE Register (Address = 0x201) [reset = 0x00]

JMODE is shown in Figure 8-59 and described in Table 8-96.

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JESD204C Mode (default: 0x00)

Figure 8-59 JMODE Register
76543210
RESERVEDJMODE
R/W-0x0R/W-0x0
Table 8-96 JMODE Register Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR/W0x0Must write default value.
5:0JMODER/W0x0Specifies the JESD204C output mode. See JESD204C Mode table.

Note: This register should only be changed when JESD_EN=0 and CAL_EN=0.

8.5.7.43 KM1 Register (Address = 0x202) [reset = 0x1F]

KM1 is shown in Figure 8-60 and described in Table 8-97.

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JESD204C K Parameter (minus 1) (default: 0x1F)

Figure 8-60 KM1 Register
76543210
KM1
R/W-0x1F
Table 8-97 KM1 Register Field Descriptions
BitFieldTypeResetDescription
7:0KM1R/W0x1FK is the number of frames per multiframe and this register must be programmed as K-1. Depending on the JMODE setting, there are constraints on the legal values of K (see K parameter in JESD204C Mode table). The default value is KM1=31, which corresponds to K=32.

Note: For modes using the 64B/66B link layer, the KM1 register is ignored and the value of K is determined from E and F (which are derived from JMODE). The effective value of K is 256*E/F.

Note: This register should only be changed when JESD_EN is 0.

8.5.7.44 JSYNC_N Register (Address = 0x203) [reset = 0x01]

JSYNC_N is shown in Figure 8-61 and described in Table 8-98.

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JESD204C Manual Sync Request (default: 0x01)

Figure 8-61 JSYNC_N Register
76543210
RESERVEDJSYNC_N
R/W-0x0R/W-0x1
Table 8-98 JSYNC_N Register Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR/W0x0Must write default value.
0JSYNC_NR/W0x1Set this bit to 0 to request JESD204C synchronization (equivalent to the SYNC~ signal being asserted). For normal operation, leave this bit set to 1.

Note: The JSYNC_N register can always generate a synchronization request, regardless of the SYNC_SEL register. However, if the selected sync pin is stuck low, you cannot de-assert the synchronization request unless you program SYNC_SEL=2.

8.5.7.45 JCTRL Register (Address = 0x204) [reset = 0x03]

JCTRL is shown in Figure 8-62 and described in Table 8-99.

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JESD204C Control (default: 0x03)

Figure 8-62 JCTRL Register
76543210
RESERVEDALT_LANESSYNC_SELSFORMATSCR
R/W-0x0R/W-0x0R/W-0x0R/W-0x1R/W-0x1
Table 8-99 JCTRL Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR/W0x0Must write default value.
4ALT_LANESR/W0x00 : Normal lane mapping (default) as shown in the JESD204C output mode section.
Lanes 0 thru L-1 are used.
1 : Alternate lane mapping (use upper lanes).
Lanes 4 to 4+L-1 are used. Lanes 0 to 3 are unused. This option is only supported when JMODE selects a mode that uses 4 or less lanes per link (L<=4). The behavior is undefined for modes that use more than 4 lanes.
3:2SYNC_SELR/W0x00 : Use the SYNCSE input for SYNC~ function (default)
1 : Use the TMSTP± input for SYNC~ function. TMSTP_RECV_EN must also be set.
2 : Do not use any SYNC~ input pin (use JSYNC_N as a software SYNC~)
1SFORMATR/W0x1Output sample format for JESD204C samples
0 : Offset binary
1 : Signed 2’s complement (default)
0SCRR/W0x10 : 8B/10B Scrambler disabled (applies only to 8B/10B modes)
1 : 8B/10B Scrambler enabled (default)

Note 1: The 8b/10b scrambler is recommended to improve spurious noise and ensure that certain sample payloads cannot prevent the JESD204C receiver from detecting incorrect code-group or lane alignment. 64B/66B modes always use scrambling. This register does not apply to 64B/66B modes.


Note: This register should only be changed when JESD_EN is 0.

8.5.7.46 JTEST Register (Address = 0x205) [reset = 0x00]

JTEST is shown in Figure 8-63 and described in Table 8-100.

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JESD204C Test Control (default: 0x00)

Figure 8-63 JTEST Register
76543210
RESERVEDJTEST
R/W-0x0R/W-0x0
Table 8-100 JTEST Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR/W0x0Must write default value.
4:0JTESTR/W0x00 : Test mode disabled. Normal operation (default)
1 : PRBS7 test mode
2 : PRBS15 test mode
3 : PRBS23 test mode
4 : Ramp test mode
5 : Transport Layer test mode
6 : D21.5 test mode
7 : K28.5 test mode*
8 : Repeated ILA test mode*
9 : Modified RPAT test mode*
10: Serial outputs held low
11: Serial outputs held high
12: RESERVED
13: PRBS9 test mode
14: PRBS31 test mode
15: Clock test pattern (0x00FF)
16: K28.7 test mode*
17-31: RESERVED

* These test modes are only supported when JMODE is selecting a mode that utilizes 8B/10B encoding.
Note: This register should only be changed when JESD_EN is 0.

8.5.7.47 DID Register (Address = 0x206) [reset = 0x00]

DID is shown in Figure 8-64 and described in Table 8-101.

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JESD204C DID Parameter (default: 0x00)

Figure 8-64 DID Register
76543210
DID
R/W-0x0
Table 8-101 DID Register Field Descriptions
BitFieldTypeResetDescription
7:0DIDR/W0x0Specifies the DID (Device ID) value that is transmitted during the second multiframe of the JESD204B ILA.

Note: This register should only be changed when JESD_EN is 0.

8.5.7.48 FCHAR Register (Address = 0x207) [reset = 0x00]

FCHAR is shown in Figure 8-65 and described in Table 8-102.

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JESD204C Frame Character (default: 0x00)

Figure 8-65 FCHAR Register
76543210
RESERVEDFCHAR
R/W-0x0R/W-0x0
Table 8-102 FCHAR Register Field Descriptions
BitFieldTypeResetDescription
7:2RESERVEDR/W0x0Must write default value.
1:0FCHARR/W0x0Specify which comma character is used to denote end-of-frame. This character is transmitted opportunistically. This only applies to modes that utilize 8B/10B encoding.
0 : Use K28.7 (default) (JESD204C compliant)
1 : Use K28.1 (not JESD204C compliant)
2 : Use K28.5 (not JESD204C compliant)
3 : Reserved

When using a JESD204C receiver, always use FCHAR=0. When using a general purpose 8B/10B receiver, the K28.7 character may cause issues. When K28.7 is combined with certain data characters, a false, misaligned comma character can result, and some receivers will re-align to the false comma. To avoid this, program FCHAR to 1 or 2.

Note: This register should only be changed when JESD_EN is 0.

8.5.7.49 JESD_STATUS Register (Address = 0x208) [reset = 0x0]

JESD_STATUS is shown in Figure 8-66 and described in Table 8-103.

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JESD204C / System Status Register

Figure 8-66 JESD_STATUS Register
76543210
RESERVEDLINK_UPSYNC_STATUSREALIGNEDALIGNEDSPLL_LOCKEDRESERVEDCPLL_LOCKED
R/W-0x0R/W-0x0R/W-0x0R/W-0x0R/W-0x0R/W-0x0R/W-0x0R/W-0x0
Table 8-103 JESD_STATUS Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0x0
6LINK_UPR/W0x0When set, indicates that the JESD204C link is up.
5SYNC_STATUSR/W0x0Returns the state of the JESD204C SYNC~ signal.
0 : SYNC~ asserted
1 : SYNC~ de-asserted
4REALIGNEDR/W0x0When high, indicates that the digital block clock, frame clock, or multiframe clock phase was realigned by SYSREF. Writing a 1 to this bit will clear it.
3ALIGNEDR/W0x0When high, indicates that the multiframe (LMFC) clock phase has been established by SYSREF. The first SYSREF event after enabling the JESD204B encoder will set this bit. Writing a 1 to this bit will clear it.
2SPLL_LOCKEDR/W0x0When high, indicates that the SerDes PLL (S-PLL) is locked.
1RESERVEDR/W0x0
0CPLL_LOCKEDR/W0x0When high, indicates that the converter PLL (C-PLL) is locked.

8.5.7.50 CH_EN Register (Address = 0x209) [reset = 0x03]

CH_EN is shown in Figure 8-67 and described in Table 8-104.

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JESD204C Channel Enable (default: 0x03)

Figure 8-67 CH_EN Register
76543210
RESERVEDSINGLE_CH_ENCD_ENAB_EN
R/W-0x0R/W-0x0R/W-0x1R/W-0x1
Table 8-104 CH_EN Register Field Descriptions
BitFieldTypeResetDescription
7:3RESERVEDR/W0x0Must write default value.
2SINGLE_CH_ENR/W0x0When set, single channel mode is enabled and channels B, C and D are disabled. AB_EN must be set to 1.
1CD_ENR/W0x1When set, the C and D channels are enabled. Set to 0 to disable channels C and D. Set this bit to enable dual channel operation.
0AB_ENR/W0x1When set, the A and B channels are enabled. Set to 0 to disable channel A and B.

Important notes:
1. You must set CAL_EN=0 and JESD_EN=0 before changing CH_EN.
2. Do not use this register to disable (power down) all channels since this state is undefined. Instead use the MODE register to power down the full device.
3. When either pair of channels is disabled, the JESD204C link will scale down the number of lanes and converters: L = ceiling(Lx/2) and M = Mx/2. If Lx is odd, tail bits are added to the end of the highest lane to pad out the frame (as per the JESD204C standard).
4. When AB_EN=0, the samples for channels C & D are placed within the JESD204C frame where the A & B samples would normally be located.

8.5.7.51 SHMODE Register (Address = 0x20F) [reset = 0x00]

SHMODE is shown in Figure 8-68 and described in Table 8-105.

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JESD204C Sync Word Mode (default: 0x00)

Figure 8-68 SHMODE Register
76543210
RESERVEDSHMODE
R/W-0x0R/W-0x0
Table 8-105 SHMODE Register Field Descriptions
BitFieldTypeResetDescription
7:2RESERVEDR/W0x0Must write default value.
1:0SHMODER/W0x0Select the mode for the 64B/66B sync word (32 bits of data per multi-block). This only applies when JMODE is selecting a 64B/66B mode.

0 : Transmit CRC-12 signal (default setting)
1 : RESERVED
2 : Transmit FEC signal
3 : RESERVED

Note: This device does not support any JESD204C command features. All command fields will be set to zero (idle headers).
Note: This register should only be changed when JESD_EN is 0.

8.5.7.52 SYNC_THRESH Register (Address = 0x210) [reset = 0x03]

SYNC_THRESH is shown in Figure 8-69 and described in Table 8-106.

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JESD204C SYNC~ Threshold (default: 0x03)

Figure 8-69 SYNC_THRESH Register
76543210
RESERVEDSYNC_THRESH
R/W-0x0R/W-0x3
Table 8-106 SYNC_THRESH Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR/W0x0Must write default value.
4:0SYNC_THRESHR/W0x3This register defines how many times the SYNC~ signal must be sampled low before the JESD204C transmitter interprets it as a synchronization request.
The SYNC~ signal is sampled by the link clock (fS/2). If SYNC~ is sampled low for SYNC_THRESH+1 consecutive clock cycles, it will be interpreted as a synchronization request. Refer to JESD204C section 8.8.2 for more details. If SYNC~ is sampled low for less than SYNC_THRESH+1 clock cycles, it is considered to be an error report and is ignored.

Note: This register should only be changed when JESD_EN is 0.
Note: Since this design does not do anything with an error reported on the SYNC~ interface, it is recommended that error reporting be disabled on the receiver and SYNC_THRESH programmed to 0. This provides the fastest response time for synchronization requests.

8.5.7.53 OVR_TH Register (Address = 0x211) [reset = 0xF2]

OVR_TH is shown in Figure 8-70 and described in Table 8-107.

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Over-range Threshold (default: 0xF2)

Figure 8-70 OVR_TH Register
76543210
OVR_TH
R/W-0xF2
Table 8-107 OVR_TH Register Field Descriptions
BitFieldTypeResetDescription
7:0OVR_THR/W0xF2This parameter defines the absolute sample level that causes the over-range outputs to be asserted. The detection level in dBFS (peak) is 20log10(OVR_TH/256) (Default: 0xF2 = 242-> -0.5dBFS)

8.5.7.54 OVR_CFG Register (Address = 0x213) [reset = 0x07]

OVR_CFG is shown in Figure 8-71 and described in Table 8-108.

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Over-range Enable / Hold Off (default: 0x07)

Figure 8-71 OVR_CFG Register
76543210
RESERVEDOVR_ENOVR_N
R/W-0x0R/W-0x0R/W-0x7
Table 8-108 OVR_CFG Register Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR/W0x0Must write default value.
3OVR_ENR/W0x0Enables over-range status output pins when set high. The ORA, ORB, ORC and ORD outputs are held low when OVR_EN is set low.
2:0OVR_NR/W0x7Program this register to adjust the pulse extension for the ORA, ORB, ORC and ORD outputs. The minimum pulse duration of the over-range outputs is 4 * 2OVR_N sampling cycles. Incrementing this field doubles the monitoring period.

8.5.7.55 INIT_STATUS Register (Address = 0x270) [reset = 0x0]

INIT_STATUS is shown in Figure 8-72 and described in Table 8-109.

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Initialization Status (read-only)

Figure 8-72 INIT_STATUS Register
76543210
RESERVEDINIT_DONE
R-0x0R-0x0
Table 8-109 INIT_STATUS Register Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR0x0
0INIT_DONER0x0Returns 1 when the initialization logic has finished initializing the device. This indicates that it is now safe to proceed with startup. No SPI transactions should be performed before INIT_DONE returns 1 (except SOFT_RESET).

8.5.7.56 LOW_POWER2 Register (Address = 0x29A) [reset = 0x0F]

LOW_POWER2 is shown in Figure 8-73 and described in Table 8-110.

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Low Power Mode 2 (default: 0x0F)

Figure 8-73 LOW_POWER2 Register
76543210
LOW_POW_MODE2
R/W-0xF
Table 8-110 LOW_POWER2 Register Field Descriptions
BitFieldTypeResetDescription
7:0LOW_POW_MODE2R/W0xFSet this register along with LOW_POWER1, LOW_POWER3 and LOW_POWER4 to enable Low Power Mode. All registers must be set together. Calibration must be performed after changing the operating mode:

0x06 : Low Power Mode (only valid when sampling rate is less than or equal to 1 GSPS)
0x0F : High Performance Mode (default)
All other values are RESERVED

Note: Must set CAL_EN to 0 and JESD_EN to 0 before changing this register.

8.5.7.57 LOW_POWER3 Register (Address = 0x29B) [reset = 0x04]

LOW_POWER3 is shown in Figure 8-74 and described in Table 8-111.

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Low Power Mode 3 (default: 0x04)

Figure 8-74 LOW_POWER3 Register
76543210
LOW_POW_MODE3
R/W-0x4
Table 8-111 LOW_POWER3 Register Field Descriptions
BitFieldTypeResetDescription
7:0LOW_POW_MODE3R/W0x4Set this register along with LOW_POWER1, LOW_POWER2 and LOW_POWER4 to enable Low Power Mode. All registers must be set together. Calibration must be performed after changing the operating mode:

0x00 : Low Power Mode (only valid when sampling rate is less than or equal to 1 GSPS)
0x04 : High Performance Mode (default)
All other values are RESERVED

Note: Must set CAL_EN to 0 and JESD_EN to 0 before changing this register.

8.5.7.58 LOW_POWER4 Register (Address = 0x29C) [reset = 0x1B]

LOW_POWER4 is shown in Figure 8-75 and described in Table 8-112.

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Low Power Mode 4 (default: 0x1B)

Figure 8-75 LOW_POWER4 Register
76543210
LOW_POW_MODE4
R/W-0x1B
Table 8-112 LOW_POWER4 Register Field Descriptions
BitFieldTypeResetDescription
7:0LOW_POW_MODE4R/W0x1BSet this register along with LOW_POWER1, LOW_POWER2 and LOW_POWER3 to enable Low Power Mode. All registers must be set together. Calibration must be performed after changing the operating mode:

0x14 : Low Power Mode (only valid when sampling rate is less than or equal to 1 GSPS)
0x1B : High Performance Mode (default)
All other values are RESERVED

Note: Must set CAL_EN to 0 and JESD_EN to 0 before changing this register.

8.5.7.59 ALARM Register (Address = 0x2C0) [reset = 0x0]

ALARM is shown in Figure 8-76 and described in Table 8-113.

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Alarm Interrupt (read-only)

Figure 8-76 ALARM Register
76543210
RESERVEDALARM
R-0x0R-0x0
Table 8-113 ALARM Register Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR0x0
0ALARMR0x0This bit returns a ‘1’ whenever any alarm occurs that is unmasked in the ALM_STATUS register. Use ALM_MASK to mask (disable) individual alarms. CAL_STATUS_SEL can be used to drive the ALARM bit onto the CALSTAT output pin to provide a hardware alarm interrupt signal.

8.5.7.60 ALM_STATUS Register (Address = 0x2C1) [reset = 0x3F]

ALM_STATUS is shown in Figure 8-77 and described in Table 8-114.

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Alarm Status (default: 0x3F, write to clear)

Figure 8-77 ALM_STATUS Register
76543210
RESERVEDFIFO_ALMSPLL_ALMLINK_ALMREALIGNED_ALMRESERVEDCLK_ALM
R/W-0x0R/W-0x1R/W-0x1R/W-0x1R/W-0x1R/W-0x1R/W-0x1
Table 8-114 ALM_STATUS Register Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR/W0x0
5FIFO_ALMR/W0x1FIFO overflow/underflow alarm: This bit is set whenever an active JESD204C lane FIFO experiences an underflow or overflow condition. Write a ‘1’ to clear this bit. To inspect which lane generated the alarm, read FIFO_LANE_ALM.
4SPLL_ALMR/W0x1S-PLL Lock Lost Alarm: This bit is set whenever the SerDes S-PLL is not locked. Write a ‘1’ to clear this bit.
3LINK_ALMR/W0x1Link Alarm: This bit is set whenever the JESD204C link is enabled, but is not in the DATA_ENC state (8B/10B modes). In 64B/66B modes, there is no DATA_ENC state, so this alarm will fire when the link first starts up, and will also fire if any event causes a FIFO/Serializer realignment. Write a ‘1’ to clear this bit.
2REALIGNED_ALMR/W0x1Realigned Alarm: This bit is set whenever SYSREF causes the internal clocks (including the LMFC/LEMC) to be realigned. Write a ‘1’ to clear this bit.
1RESERVEDR/W0x1
0CLK_ALMR/W0x1Clock Alarm: This bit can be used to detect an upset to the internal digital block and JESD204C clocks. This bit is set whenever the internal clock dividers for the A and B channels do not match the C and D channels. Write a ‘1’ to clear this bit. Refer to the alarm section for the proper usage of this register.

Note: After power-on reset or soft-reset, all alarm bits are set to ‘1.’
Note: When JESD_EN=0, all alarms (except CLK_ALM) are undefined. It is recommended that the user clears the alarms after setting JESD_EN=1.

8.5.7.61 ALM_MASK Register (Address = 0x2C2) [reset = 0x3F]

ALM_MASK is shown in Figure 8-78 and described in Table 8-115.

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Alarm Mask Register (default: 0x3F)

Figure 8-78 ALM_MASK Register
76543210
RESERVEDMASK_FIFO_ALMMASK_PLL_ALMMASK_LINK_ALMMASK_REALIGNED_ALMRESERVEDMASK_CLK_ALM
R/W-0x0R/W-0x1R/W-0x1R/W-0x1R/W-0x1R/W-0x1R/W-0x1
Table 8-115 ALM_MASK Register Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR/W0x0Must write default value.
5MASK_FIFO_ALMR/W0x1When set, FIFO_ALM is masked and will not impact the ALARM register bit.
4MASK_PLL_ALMR/W0x1When set, PLL_ALM is masked and will not impact the ALARM register bit.
3MASK_LINK_ALMR/W0x1When set, LINK_ALM is masked and will not impact the ALARM register bit.
2MASK_REALIGNED_ALMR/W0x1When set, REALIGNED_ALM is masked and will not impact the ALARM register bit.
1RESERVEDR/W0x1Must write default value.
0MASK_CLK_ALMR/W0x1When set, CLK_ALM is masked and will not impact the ALARM register bit.

8.5.7.62 FIFO_LANE_ALM Register (Address = 0x2C4) [reset = 0xFF]

FIFO_LANE_ALM is shown in Figure 8-79 and described in Table 8-116.

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FIFO Overflow/Underflow Alarm (default: 0xFF)

Figure 8-79 FIFO_LANE_ALM Register
76543210
FIFO_LANE_ALM
R/W-0xFF
Table 8-116 FIFO_LANE_ALM Register Field Descriptions
BitFieldTypeResetDescription
7:0FIFO_LANE_ALMR/W0xFFFIFO_LANE_ALM[i] is set if the FIFO for lane i experiences overflow or underflow. Use this register to determine which lane(s) generated an alarm. Writing a ‘1’ to any bit in this register will clear the alarm (the alarm may immediately trip again if the overflow/underflow condition persists). Writing a ‘1’ to the FIFO_ALM register will clear all bits of this register.

8.5.7.63 OFS0 Register (Address = 0x330) [reset = 0x0]

OFS0 is shown in Figure 8-80 and described in Table 8-117.

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Offset Adjustment for ADC0 (default from Fuse ROM)

Figure 8-80 OFS0 Register
15141312111098
RESERVEDOFS0
R/W-0x0R/W-0x0
76543210
OFS0
R/W-0x0
Table 8-117 OFS0 Register Field Descriptions
BitFieldTypeResetDescription
15:12RESERVEDR/W0x0Must write default value.
11:0OFS0R/W0x0Offset adjustment value applied to ADC0. The format is unsigned.

Important note: Do not access any OFS* registers if the calibration system is performing offset calibration.

Case 1: If CAL_BGOS or CAL_BG is 0 and CAL_OS is 1, you may access OFS* registers after FG_DONE goes high.
Case 2: If CAL_BG=1 and CAL_BGOS=1, you should not access the OFS* registers. For background calibration without continuous offset calibration, set CAL_OS to 1 and CAL_BG to 1, but keep CAL_BGOS set to 0. This will still calibrate the offset of the spare ADC cores during the foreground offset calibration step.
Case 3: If none of the above conditions apply, you may access the OFS* registers without waiting.

8.5.7.64 OFS1 Register (Address = 0x332) [reset = 0x0]

OFS1 is shown in Figure 8-81 and described in Table 8-118.

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Offset Adjustment for ADC1 (default from Fuse ROM)

Figure 8-81 OFS1 Register
15141312111098
RESERVEDOFS1
R/W-0x0R/W-0x0
76543210
OFS1
R/W-0x0
Table 8-118 OFS1 Register Field Descriptions
BitFieldTypeResetDescription
15:12RESERVEDR/W0x0Must write default value.
11:0OFS1R/W0x0Offset adjustment value applied to ADC1.

8.5.7.65 OFS2A Register (Address = 0x334) [reset = 0x0]

OFS2A is shown in Figure 8-82 and described in Table 8-119.

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Offset Adjustment for ADC2 (INA±) (default from Fuse ROM)

Figure 8-82 OFS2A Register
15141312111098
RESERVEDOFS2A
R/W-0x0R/W-0x0
76543210
OFS2A
R/W-0x0
Table 8-119 OFS2A Register Field Descriptions
BitFieldTypeResetDescription
15:12RESERVEDR/W0x0Must write default value.
11:0OFS2AR/W0x0Offset adjustment value applied to ADC2 when sampling INA±.

8.5.7.66 OFS2B Register (Address = 0x336) [reset = 0x0]

OFS2B is shown in Figure 8-83 and described in Table 8-120.

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Offset Adjustment for ADC2 (INB±) (default from Fuse ROM)

Figure 8-83 OFS2B Register
15141312111098
RESERVEDOFS2B
R/W-0x0R/W-0x0
76543210
OFS2B
R/W-0x0
Table 8-120 OFS2B Register Field Descriptions
BitFieldTypeResetDescription
15:12RESERVEDR/W0x0Must write default value.
11:0OFS2BR/W0x0Offset adjustment value applied to ADC2 when sampling INB±.

8.5.7.67 OFS3C Register (Address = 0x338) [reset = 0x0]

OFS3C is shown in Figure 8-84 and described in Table 8-121.

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Offset Adjustment for ADC3 (INC±) (default from Fuse ROM)

Figure 8-84 OFS3C Register
15141312111098
RESERVEDOFS3C
R/W-0x0R/W-0x0
76543210
OFS3C
R/W-0x0
Table 8-121 OFS3C Register Field Descriptions
BitFieldTypeResetDescription
15:12RESERVEDR/W0x0Must write default value.
11:0OFS3CR/W0x0Offset adjustment value applied to ADC3 when sampling INC±.

8.5.7.68 OFS3D Register (Address = 0x33A) [reset = 0x0]

OFS3D is shown in Figure 8-85 and described in Table 8-122.

Return to the Summary Table.

Offset Adjustment for ADC3 (IND±) (default from Fuse ROM)

Figure 8-85 OFS3D Register
15141312111098
RESERVEDOFS3D
R/W-0x0R/W-0x0
76543210
OFS3D
R/W-0x0
Table 8-122 OFS3D Register Field Descriptions
BitFieldTypeResetDescription
15:12RESERVEDR/W0x0Must write default value.
11:0OFS3DR/W0x0Offset adjustment value applied to ADC3 when sampling IND±.

8.5.7.69 OFS4 Register (Address = 0x33C) [reset = 0x0]

OFS4 is shown in Figure 8-86 and described in Table 8-123.

Return to the Summary Table.

Offset Adjustment for ADC4 (default from Fuse ROM)

Figure 8-86 OFS4 Register
15141312111098
RESERVEDOFS4
R/W-0x0R/W-0x0
76543210
OFS4
R/W-0x0
Table 8-123 OFS4 Register Field Descriptions
BitFieldTypeResetDescription
15:12RESERVEDR/W0x0Must write default value.
11:0OFS4R/W0x0Offset adjustment value applied to ADC4.

8.5.7.70 OFS5 Register (Address = 0x33E) [reset = 0x0]

OFS5 is shown in Figure 8-87 and described in Table 8-124.

Return to the Summary Table.

Offset Adjustment for ADC5 (default from Fuse ROM)

Figure 8-87 OFS5 Register
15141312111098
RESERVEDOFS5
R/W-0x0R/W-0x0
76543210
OFS5
R/W-0x0
Table 8-124 OFS5 Register Field Descriptions
BitFieldTypeResetDescription
15:12RESERVEDR/W0x0Must write default value.
11:0OFS5R/W0x0Offset adjustment value applied to ADC5.

8.5.7.71 GAIN0 Register (Address = 0x360) [reset = 0x0]

GAIN0 is shown in Figure 8-88 and described in Table 8-125.

Return to the Summary Table.

Fine Gain Adjust for ADC0 (default from Fuse ROM)

Figure 8-88 GAIN0 Register
76543210
RESERVEDGAIN0
R/W-0x0R/W-0x0
Table 8-125 GAIN0 Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR/W0x0Must write default value.
4:0GAIN0R/W0x0Fine gain adjustment for ADC0.

8.5.7.72 GAIN1 Register (Address = 0x361) [reset = 0x0]

GAIN1 is shown in Figure 8-89 and described in Table 8-126.

Return to the Summary Table.

Fine Gain Adjust for ADC1 (default from Fuse ROM)

Figure 8-89 GAIN1 Register
76543210
RESERVEDGAIN1
R/W-0x0R/W-0x0
Table 8-126 GAIN1 Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR/W0x0Must write default value.
4:0GAIN1R/W0x0Fine gain adjustment for ADC1.

8.5.7.73 GAIN2A Register (Address = 0x362) [reset = 0x0]

GAIN2A is shown in Figure 8-90 and described in Table 8-127.

Return to the Summary Table.

Fine Gain Adjust for ADC2 (INA±) (default from Fuse ROM)

Figure 8-90 GAIN2A Register
76543210
RESERVEDGAIN2A
R/W-0x0R/W-0x0
Table 8-127 GAIN2A Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR/W0x0Must write default value.
4:0GAIN2AR/W0x0Fine gain adjustment for ADC2 when sampling INA±.

8.5.7.74 GAIN2B Register (Address = 0x363) [reset = 0x0]

GAIN2B is shown in Figure 8-91 and described in Table 8-128.

Return to the Summary Table.

Fine Gain Adjust for ADC2 (INB±) (default from Fuse ROM)

Figure 8-91 GAIN2B Register
76543210
RESERVEDGAIN2B
R/W-0x0R/W-0x0
Table 8-128 GAIN2B Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR/W0x0Must write default value.
4:0GAIN2BR/W0x0Fine gain adjustment for ADC2 when sampling INB±.

8.5.7.75 GAIN3C Register (Address = 0x364) [reset = 0x0]

GAIN3C is shown in Figure 8-92 and described in Table 8-129.

Return to the Summary Table.

Fine Gain Adjust for ADC3 (INC±) (default from Fuse ROM)

Figure 8-92 GAIN3C Register
76543210
RESERVEDGAIN3C
R/W-0x0R/W-0x0
Table 8-129 GAIN3C Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR/W0x0Must write default value.
4:0GAIN3CR/W0x0Fine gain adjustment for ADC3 when sampling INC±.

8.5.7.76 GAIN3D Register (Address = 0x365) [reset = 0x0]

GAIN3D is shown in Figure 8-93 and described in Table 8-130.

Return to the Summary Table.

Fine Gain Adjust for ADC3 (IND±) (default from Fuse ROM)

Figure 8-93 GAIN3D Register
76543210
RESERVEDGAIN3D
R/W-0x0R/W-0x0
Table 8-130 GAIN3D Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR/W0x0Must write default value.
4:0GAIN3DR/W0x0Fine gain adjustment for ADC3 when sampling IND±.

8.5.7.77 GAIN4 Register (Address = 0x366) [reset = 0x0]

GAIN4 is shown in Figure 8-94 and described in Table 8-131.

Return to the Summary Table.

Fine Gain Adjust for ADC4 (default from Fuse ROM)

Figure 8-94 GAIN4 Register
76543210
RESERVEDGAIN4
R/W-0x0R/W-0x0
Table 8-131 GAIN4 Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR/W0x0Must write default value.
4:0GAIN4R/W0x0Fine gain adjustment for ADC4.

8.5.7.78 GAIN5 Register (Address = 0x367) [reset = 0x0]

GAIN5 is shown in Figure 8-95 and described in Table 8-132.

Return to the Summary Table.

Fine Gain Adjust for ADC5 (default from Fuse ROM)

Figure 8-95 GAIN5 Register
76543210
RESERVEDGAIN5
R/W-0x0R/W-0x0
Table 8-132 GAIN5 Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR/W0x0Must write default value.
4:0GAIN5R/W0x0Fine gain adjustment for ADC5.
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