Device power consumption can be reduced at the tradeoff of performance by programming the device into the Low Power Mode. This mode is only available when operating at 1 GSPS or less and is recommended to only be used for 1^st Nyquist zone applications. The default operating mode is High Performance Mode which is enabled by the default register values. Table 7-12 shows the register writes to switch between the lowest power configuration of Low Power Mode and High Performance Mode. These writes should only be performed when CAL_EN is set to 0 and JESD_EN is set to 0.

The magnitude of the glitch during the transition between ADC cores during background calibration and low power background calibration is affected by the setting of the LOW_POWER3 register setting (Address = 0x29B). A lower power can be traded off vs larger glitch magnitude. The ADC output during the transition between ADC cores for low power mode is shown in Figure 7-12 and the power dissipation change vs LOW_POWER3 setting is shown in Figure 7-13. A setting of 4 reduces the glitch to the same magnitude as high performance mode.

Figure 7-12 Background Calibration Core Transition In Low Power Mode

Figure 7-13 Power Dissipation Change vs LOW_POWER3 register setting

In low power background calibration mode, the timing of the ADC transition can be controlled by setting register LP_TRIG = 1. The ADC transition will occur in the ADC output data between 500 and 1000 ADC sample clocks after triggering by the CALTRIG ball or SPI write to CAL_SOFT_TRIG register (Address = 0x6C).

Foreground calibration mode has no ADC core transitions and no glitch.