There are many critical signals that require specific care during board design:

1. Analog input signals
2. CLK, SE_CLK and SYSREF
3. JESD204C data outputs
4. Power connections
5. Ground connections

The analog input signals, clock signals and JESD204C data outputs must be routed for excellent signal quality at high frequencies, but should also be routed for maximum isolation from each other. Use the following general practices:

1. Route using loosely coupled 100Ω differential traces when possible. This routing minimizes impact of corners and length-matching serpentines on pair impedance. SE_CLK should be routed as a coplanar waveguide or as a stripline on an internal layer with sufficient via-fencing to prevent coupling.
2. Provide adequate pair-to-pair spacing to minimize crosstalk, especially with loosely coupled differential traces. Tightly coupled differential traces may be used to reduce self-radiated noise or to improve neighboring trace noise immunity when adequate spacing cannot be provided.
3. Provide adequate ground plane pour spacing to minimize coupling with the high-speed traces. Any ground plane pour must have sufficient via connections to the main ground plane of the board. Do not use floating or poorly connected ground pours.
4. Use smoothly radiused corners. Avoid 45° or 90° bends to reduce impedance mismatches.
5. Incorporate ground plane cutouts at component landing pads to avoid impedance discontinuities at these locations. Cut-out below the landing pads on one or multiple ground planes to achieve a pad size or stackup height that achieves the needed 50Ω, single-ended impedance.
6. Avoid routing traces near irregularities in the reference ground planes. Irregularities include cuts in the ground plane or ground plane clearances associated with power and signal vias and through-hole component leads.
7. Provide symmetrically located ground tie vias adjacent to any high-speed signal vias at an appropriate spacing as determined by the maximum frequency the trace transports (<< λ_MIN/8).
8. When high-speed signals must transition to another layer using vias, transition as far through the board as possible (top to bottom is best case) to minimize via stubs on top or bottom of the vias. If layer selection is not flexible, use back-drilled or buried, blind vias to eliminate stubs. Always place ground vias close to the signal vias when transitioning between layers to provide a nearby ground return path.

Attention must be given to potential coupling between JESD204C data output routing and the analog input routing. Switching noise from the JESD204C outputs can couple into the analog input traces and show up as wideband noise due to the high input bandwidth of the ADC. Route the JESD204C data outputs on a separate layer from the ADC input traces to avoid noise coupling (not shown in the Layout Example section). Tightly coupled traces can also be used to reduce noise coupling.

Impedance mismatch between the CLK± input pins and the clock source can result in reduced amplitude of the clock signal at the ADC CLK± pins due to signal reflections or standing waves. A reduction in the clock amplitude may degrade ADC noise performance, especially at high input frequencies. To avoid this, keep the clock source close to the ADC (as shown in the Layout Example section) or implement impedance matching at the ADC CLK± input pins.

In addition, TI recommends performing signal quality simulations of the critical signal traces before committing to fabrication. Insertion loss, return loss, and time domain reflectometry (TDR) evaluations should be done.

The power and ground connections for the device are also very important. These rules must be followed:

1. Provide low-resistance connection paths to all power and ground pins.
2. Use multiple power layers if necessary to access all pins.
3. Avoid narrow isolated paths that increase connection resistance.
4. Use a signal-ground-power board stackup to maximum capacitance between the ground and power planes.