ZHCSOI5A October   2021  – November 2024 ADC12DJ1600 , ADC12QJ1600 , ADC12SJ1600

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Device Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: DC Specifications
    6. 6.6  Electrical Characteristics: Power Consumption
    7. 6.7  Electrical Characteristics: AC Specifications
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
        1. 7.3.1.1 Analog Input Protection
        2. 7.3.1.2 Full-Scale Voltage (VFS) Adjustment
        3. 7.3.1.3 Analog Input Offset Adjust
        4. 7.3.1.4 ADC Core
          1. 7.3.1.4.1 ADC Theory of Operation
          2. 7.3.1.4.2 ADC Core Calibration
          3. 7.3.1.4.3 Analog Reference Voltage
          4. 7.3.1.4.4 ADC Over-range Detection
          5. 7.3.1.4.5 Code Error Rate (CER)
      2. 7.3.2 Temperature Monitoring Diode
      3. 7.3.3 Timestamp
      4. 7.3.4 Clocking
        1. 7.3.4.1 Converter PLL (C-PLL) for Sampling Clock Generation
        2. 7.3.4.2 LVDS Clock Outputs (PLLREFO±, TRIGOUT±)
        3. 7.3.4.3 Optional CMOS Clock Outputs (ORC, ORD)
        4. 7.3.4.4 SYSREF for JESD204C Subclass-1 Deterministic Latency
          1. 7.3.4.4.1 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          2. 7.3.4.4.2 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
      5. 7.3.5 JESD204C Interface
        1. 7.3.5.1  Transport Layer
        2. 7.3.5.2  Scrambler
        3. 7.3.5.3  Link Layer
        4. 7.3.5.4  8B or 10B Link Layer
          1. 7.3.5.4.1 Data Encoding (8B or 10B)
          2. 7.3.5.4.2 Multiiframes and the Local Multiframe Clock (LMFC)
          3. 7.3.5.4.3 Code Group Synchronization (CGS)
          4. 7.3.5.4.4 Initial Lane Alignment Sequence (ILAS)
          5. 7.3.5.4.5 Frame and Multiframe Monitoring
        5. 7.3.5.5  64B or 66B Link Layer
          1. 7.3.5.5.1 64B or 66B Encoding
          2. 7.3.5.5.2 Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)
            1. 7.3.5.5.2.1 Block, Multiblock and Extended Multiblock Alignment using Sync Header
              1. 7.3.5.5.2.1.1 Cyclic Redundancy Check (CRC) Mode
              2. 7.3.5.5.2.1.2 Forward Error Correction (FEC) Mode
          3. 7.3.5.5.3 Initial Lane Alignment
          4. 7.3.5.5.4 Block, Multiblock and Extended Multiblock Alignment Monitoring
        6. 7.3.5.6  Physical Layer
          1. 7.3.5.6.1 SerDes Pre-Emphasis
        7. 7.3.5.7  JESD204C Enable
        8. 7.3.5.8  Multi-Device Synchronization and Deterministic Latency
        9. 7.3.5.9  Operation in Subclass 0 Systems
        10. 7.3.5.10 Alarm Monitoring
          1. 7.3.5.10.1 Clock Upset Detection
          2. 7.3.5.10.2 FIFO Upset Detection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Low Power Mode and High Performance Mode
      2. 7.4.2 JESD204C Modes
        1. 7.4.2.1 JESD204C Transport Layer Data Formats
        2. 7.4.2.2 64B or 66B Sync Header Stream Configuration
        3. 7.4.2.3 Redundant Data Mode (Alternate Lanes)
      3. 7.4.3 Power-Down Modes
      4. 7.4.4 Test Modes
        1. 7.4.4.1 Serializer Test-Mode Details
        2. 7.4.4.2 PRBS Test Modes
        3. 7.4.4.3 Clock Pattern Mode
        4. 7.4.4.4 Ramp Test Mode
        5. 7.4.4.5 Short and Long Transport Test Mode
          1. 7.4.4.5.1 Short Transport Test Pattern
        6. 7.4.4.6 D21.5 Test Mode
        7. 7.4.4.7 K28.5 Test Mode
        8. 7.4.4.8 Repeated ILA Test Mode
        9. 7.4.4.9 Modified RPAT Test Mode
      5. 7.4.5 Calibration Modes and Trimming
        1. 7.4.5.1 Foreground Calibration Mode
        2. 7.4.5.2 Background Calibration Mode
        3. 7.4.5.3 Low-Power Background Calibration (LPBG) Mode
      6. 7.4.6 Offset Calibration
      7. 7.4.7 Trimming
    5. 7.5 Programming
      1. 7.5.1 Using the Serial Interface
      2. 7.5.2 SCS
      3. 7.5.3 SCLK
      4. 7.5.4 SDI
      5. 7.5.5 SDO
      6. 7.5.6 Streaming Mode
      7. 7.5.7 SPI_Register_Map Registers
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Light Detection and Ranging (LiDAR) Digitizer
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Analog Front-End Requirements
          2. 8.2.1.2.2 Calculating Clock and SerDes Frequencies
        3. 8.2.1.3 Application Curves
    3. 8.3 Initialization Set Up
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 Power Sequencing
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Device Support
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 静电放电警告
    6. 9.6 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息
Initial Lane Alignment Sequence (ILAS)

After the transmitter detects the SYNC signal deassert (logic '0' to logic '1' transition), the transmitter waits until its next LMFC edge to start sending the initial lane alignment sequence (ILAS). The ILAS consists of four multiframes each containing a predetermined sequence. The receiver searches for the start of the ILAS to determine the frame and multiframe boundaries. Each multiframe of the ILAS starts with a /R/ character (K28.0) and ends with a /A/ character (K28.3) and either can be used to detect the boundary of a multiframe. Each lane starts buffering its data in the elastic buffer once the ILAS reaches the receiver, starting with the /R/ character, until all receivers have received the ILAS and subsequently release the ILAS from all lanes at the same time to align the lanes. The elastic buffer release point is chosen to avoid ambiguity in the release of the data caused by variation in the data delay (arrival of the ILAS at the receiver for each lane). The second multiframe of the ILAS contains configuration parameters for the JESD204C link configuration that can be used by the receiver to verify that the transmitter and receiver configurations match.