7.2.1 Reference Input (V_REF)

The externally supplied reference voltage (V_REF) sets the analog input range. The ADC141S628-Q1 will operate with V_REF in the range of 1 V to V_A.

Operation with V_REF below 1 V is also possible with slightly diminished performance. As V_REF is reduced, the range of acceptable analog input voltages is reduced. The peak-to-peak input range is limited to (V_REF).

Reducing V_REF also reduces the size of the least significant bit (LSB). The size of one LSB is equal to [(V_REF) / 2n], where n is 14. When the LSB size goes below the noise floor of the ADC141S628-Q1, the noise spans an increasing number of codes and overall performance suffers. For example, the SNR from dynamic signals degrades, while code uncertainty increases in DC measurements. Because the noise is Gaussian in nature, the effects of this noise can be reduced by averaging the results of a number of consecutive conversions.

Additionally, because offset and gain errors are specified in LSB, any offset or gain errors inherent in the ADC increase in terms of LSB size as V_REF is reduced.

V_REF and analog inputs (+IN and –IN) are connected to the capacitor array through a switch matrix when the input is sampled. Hence, I_REF, I_+IN, and I_–IN are a series of transient spikes that occur at a frequency dependent on the operating sample rate of the ADC141S628-Q1.

I_REF changes only slightly with temperature. See Figure 29 for additional details.

7.2.2 Analog Signal Inputs

The ADC141S628-Q1 has a pseudo-differential input where the effective input voltage that is digitized is (+IN) – (–IN) and –IN is restricted to be close to ground. By using this differential input, small signals common to both inputs are rejected. As shown in Figure 31, noise is rejected well at low frequencies where the common-mode rejection ratio (CMRR) is 90 dB. As the frequency increases to 1 MHz, the CMRR rolls off to 40 dB.

Figure 31. Analog Input CMRR vs Frequency

The current required to recharge the input sampling capacitor causes voltage spikes at +IN and –IN. Do not try to filter out these noise spikes. Rather, ensure that the transients settle out during the acquisition period.

7.2.3 Pseudo-Differential Operation

For pseudo-differential operation, the noninverting input (+IN) of the ADC141S628-Q1 can be driven with a signal that goes from GND to a voltage equal to or less than V_REF. Connect the inverting input (–IN) to either the local GND or the remote sensor ground. This connection allows +IN a maximum swing range of ground to V_REF. Figure 32 shows the ADC141S628-Q1 being driven by a full-scale single-ended source.

Figure 32. Single-Ended Input

7.2.4 Serial Digital Interface

The ADC141S628-Q1 communicates via a synchronous 3-wire serial interface as described in Figure 1 or re-shown in Figure 33 for convenience. CS, chip-select bar, initiates conversions and frames the serial data transfers. SCLK (serial clock) controls both the conversion process and the timing of serial data. D_OUT is the serial data output pin, where a conversion result is sent as a serial data stream, MSB first.

A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS. The ADC141S628-Q1 D_OUT pin is in a high-impedance state when CS is high and is active when CS is low; thus, CS acts as an output enable.

The ADC141S628-Q1 samples the input upon the assertion of CS. Assertion is defined as bringing the CS pin to a logic low state. For the first 15 periods of the SCLK following the assertion of CS, the ADC141S628-Q1 is converting the analog input voltage. On the 16th falling edge of SCLK, the ADC141S628-Q1 enters acquisition (t_ACQ) mode. For the next three periods of SCLK, the ADC141S628-Q1 is operating in acquisition mode where the ADC input is tracking the analog input signal applied across +IN and –IN. During acquisition mode, the ADC141S628-Q1 is consuming a minimal amount of power.

The ADC141S628-Q1 can enter conversion mode (t_CONV) under three different conditions. The first condition involves CS going low (asserted) with SCLK high. In this case, the ADC141S628-Q1 enters conversion mode on the first falling edge of SCLK after CS is asserted. In the second condition, CS goes low with SCLK low. Under this condition, the ADC141S628-Q1 automatically enters conversion mode and the falling edge of CS is seen as the first falling edge of SCLK. In the third condition, CS and SCLK go low simultaneously and the ADC141S628-Q1 enters conversion mode. While there is no timing restriction with respect to the falling edges of CS and SCLK, there is a minimum and maximum setup time requirements for the falling edge of CS with respect to the rising edge of SCLK. See Figure 5 for more information.

Figure 33. ADC141S628-Q1 Single Conversion Timing Diagram

7.2.5 CS Input

The CS (chip-select bar) input is active low and is TTL- and CMOS-compatible. The ADC141S628-Q1 enters conversion mode when CS is asserted and the SCLK pin is in a logic low state. When CS is high, the ADC141S628-Q1 is always in acquisition mode and thus consuming the minimum amount of power. Because CS must be asserted to begin a conversion, the sample rate of the ADC141S628-Q1 is equal to the assertion rate of CS.

Proper operation requires that the fall of CS not occur simultaneously with a rising edge of SCLK. If the fall of CS occurs during the rising edge of SCLK, the data may be clocked out one bit early. Whether or not the data are clocked out early depends upon how close the CS transition is to the SCLK transition, the device temperature, and the characteristics of the individual device. To ensure that the MSB is always clocked out at a given time (the third falling edge of SCLK), the fall of CS must always meet the timing requirement specified in the ADC141S628-Q1 Timing Requirements table.

7.2.6 SCLK Input

The SCLK (serial clock) is used as the conversion clock to shift out the conversion result. SCLK is TTL- and CMOS-compatible. Internal settling time requirements limit the maximum clock frequency while internal capacitor leakage limits the minimum clock frequency. The ADC141S628-Q1 offers specified performance with the clock rates indicated in the ADC141S628-Q1 Converter Electrical Characteristics table.

The ADC141S628-Q1 enters acquisition mode on the 16th falling edge of SCLK during a conversion frame. Assuming that the LSB is clocked into a controller on the 16th rising edge of SCLK, there is a minimum acquisition time period that must be met before a new conversion frame can begin. Other than the 16th rising edge of SCLK that was used to latch the LSB into a controller, there is no requirement for the SCLK to transition during acquisition mode. Therefore, SCLK can be idle after the LSB is latched into the controller.

7.2.7 Data Output

The data output format of the ADC141S628-Q1 is straight binary, as shown in Figure 34. This figure indicates the ideal output code for a given input voltage and does not include the effects of offset, gain error, linearity errors, or noise. Each data output bit is output on the falling edges of SCLK. The first and second SCLK falling edges clock out leading zeros while the third to 16th SCLK falling edges clock out the conversion result, MSB first.

Figure 34. ADC Output vs Input

While most receiving systems capture the digital output bits on the rising edges of SCLK, the falling edges of SCLK may be used to capture the conversion result if the minimum hold time for D_OUT is acceptable. See Figure 4 for D_OUT hold (t_DH) and access (t_DA) times.

D_OUT is enabled on the falling edge of CS and disabled on the rising edge of CS. If CS is raised prior to the 16th falling edge of SCLK, the current conversion is aborted and D_OUT goes into its high impedance state. A new conversion begins when CS is driven LOW.

7.3.1 Power Consumption

The architecture, design, and fabrication process allow the ADC141S628-Q1 to operate at conversion rates up to 200 kSPS while consuming very little power. The ADC141S628-Q1 consumes the least amount of power while operating in acquisition (power-down) mode. For applications where power consumption is critical, operate the ADC141S628-Q1 in acquisition mode as often as the application tolerates. To further reduce power consumption, stop the SCLK while CS is high.